Abstract: A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.

Abstract: A screen for a glazed area such as a window or a door to reduce heat transfer has a board with a light reflective face and top and bottom tracks to permit attachment to the wall around a window or door opening. In a variant a transparent fluted plastic board has frame extrusions on the top and bottom edge to close the flutes and is supported in top and bottom tracks enabling the assembly to be lifted in and out and slid laterally. This variant can be installed in a window opening and exerts a double glazing and noise reduction effect.

Abstract: Anti-bacterial composition comprising an admixture of an organic acid (excluding acetate, propionate and butyrate) together with a coumarin or coumarin glycoside. Preferred organic acids include lactate, citrate and benzoate, especially L-lactate. Preferred coumarins are esculetin, scopoletin, imbelliferone and Coumarin (1,2-benzopyrone). The composition, which is effective against E. coli 0157, Salmonella, Listeria, Campylobacter and MRSA, can be used to disinfect buildings or instruments and in food preparation, e.g., as a vegetable wash.

Abstract: A shift register page buffer for use in an array of multiple bits-per-cell flash EEPROM memory cells so as to render page mode programming and reading is provided. A sensing logic circuit (26,27) is used to selectively and sequentially compare array bit line voltages with each of a plurality of target reference cell bit line voltages. Shift register circuit (300) is responsive to the sensing logic circuit for sequentially storing either a low or high logic level after each comparison of the bit line voltages with one of the plurality of target reference voltages. Each of the shift register circuits is formed of series-connected latch circuits (302-308), each having inputs and outputs. A switching transistor (N5) is interconnected between the sensing logic circuit and the latch circuits and is responsive to a corresponding output of the latch circuits for selectively passing the logic signal from the sensing circuit means to the input of the latch circuits.

Abstract: An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and an erase verify reference cell array for generating an upper erased state threshold voltage level. A pre-charge circuit (36a) is used to pre-charge all the array bit lines to a predetermined potential prior to a programming back operation. A reference generator circuit (134) is used for generating a reference output voltage corresponding to a lower erased state threshold voltage level. A switching circuit (P1, N1) is used to selectively disconnect a program current source of approximately 5 .mu.A from the selected certain ones of the columns of array bit lines containing the selected memory core cells which have been correctly programmed back.