Abstract: Technologies are generally described for concurrent activation of multiple illumination sources to analyze a sample. A controller may be configured to activate the illumination sources substantially simultaneously, where a current or voltage of each activated illumination source is modulated at a different frequency by respective circuit drivers of the controller. Each activated illumination source may be configured to illuminate the sample with light at a different emission wavelength, and one or more detectors may be configured to detect a composite signal from the sample in response to the illumination. The composite signal may include multiple returned signals, where each returned signal corresponds to light emitted from one of the activated illumination sources at a respective emission wavelength. One or more filters, each associated with a respective modulation frequency of one activated illumination source, may be configured to extract each returned signal from the composite signal for analysis.

Abstract: Technologies are generally described for concurrent activation of multiple illumination sources to analyze a sample. A controller may be configured to activate the illumination sources substantially simultaneously, where a current or voltage of each activated illumination source is modulated at a different frequency by respective circuit drivers of the controller. Each activated illumination source may be configured to illuminate the sample with light at a different emission wavelength, and one or more detectors may be configured to detect a composite signal from the sample in response to the illumination. The composite signal may include multiple returned signals, where each returned signal corresponds to light emitted from one of the activated illumination sources at a respective emission wavelength. One or more filters, each associated with a respective modulation frequency of one activated illumination source, may be configured to extract each returned signal from the composite signal for analysis.

Abstract: The present invention provides devices and methods for testing the electrical performance of thin-film transistor backplane arrays and protecting thin-films during testing and handling.

Abstract: The present invention provides devices capable of testing the electrical performance of thin-film transistor backplane arrays and methods for their use.

Abstract: The present invention provides devices and methods for testing the electrical performance of thin-film transistor backplane arrays and protecting thin-films during testing and handling.

Abstract: The present invention provides devices capable of testing the electrical performance of thin-film transistor backplane arrays and methods for their use.

Abstract: A field emission source comprising a first conductive region, a layer of nanotubes deposited on the first conductive region, and a second conductive region placed over and spaced from the nanotube coated first conductive region. After the device structure is fabricated, a laser beam is used to dislodge one end of the nanotube from the first conductive surface and an electric field is simultaneously applied to point the freed end of the nanotube at the second conductive region.

Abstract: A vacuum gap dielectric field emission triode and a method of fabrication include a conductive layer positioned on a supporting substrate and an emitter positioned on the conductive layer. A gate metal layer electrically separated from the conductive layer defines a metal bridge gate surrounding the emitter and separated from the emitter by a substantially fixed distance. The gate metal layer defines a gate opening through the metal bridge gate overlying the emitter. An anode is positioned in spaced relationship to the gate metal layer and the triode is sealed in a substantial vacuum so that the emitter is separated from the metal bridge by the substantial vacuum and the metal bridge is separated from the anode by the substantial vacuum.

Abstract: A field emission source comprising a first conductive region, a layer of nanotubes deposited on the first conductive region, and a second conductive region placed over and spaced from the nanotube coated first conductive region. After the device structure is fabricated, a laser beam is used to dislodge one end of the nanotube from the first conductive surface and an electric field is simultaneously applied to point the freed end of the nanotube at the second conductive region.

Abstract: A field emission device (100, 200, 300, 400, 500) includes a substrate (110, 210, 310, 410, 510), a cathode (115, 215, 315, 415, 515) formed thereon, a plurality of electron emitters (170, 270, 370, 470, 570) and a plurality of gate electrodes (150, 250, 350, 450, 550) proximately disposed to the plurality of electron emitters (170, 270, 370, 470, 570) for effecting electron emission therefrom, a dielectric layer (140, 240, 340, 440, 540) having a major surface (143, 243, 343, 443, 543), a surface passivation layer (190, 290, 390, 490, 590) formed on the major surface (143, 243, 343, 443, 543), and an anode (180, 280, 380, 480, 580) spaced from the gate electrodes (250, 350, 450, 550).

Abstract: A portable electronic device with virtual image display including a semiconductor array providing a real image and an optical system mounted to receive the real image and produce a virtual image at a viewing aperture. Electronics are associated with the array to produce real images in accordance with messages received by a data source such as a communication receiver. The display is sufficiently small to mount in a hand held microphone for viewing by the operator while using the microphone.

Abstract: A field emission display (100, 200, 300) includes a plurality of offset phosphors (126) and a cathode plate (110). Cathode plate (110) has a plurality of non-electron-emissive structures (112), a plurality of electron-emissive pixels (108), and a plurality of focusing electrodes (106). Offset phosphors (126) are aligned one each with non-electron-emissive structures (112) of cathode plate (110). Focusing electrodes (106) are disposed to cause a plurality of emission currents (134), which are generated by electron-emissive pixels (108), to be directed one each toward offset phosphors (126). Ions liberated from offset phosphors (126) are received by non-electron-emissive structures (112) of cathode plate (110), thereby ameliorating ion bombardment of electron-emissive pixels (108).

Abstract: A portable communications receiver with virtual image display including a semiconductor array providing a real image and an optical system mounted to receive the real image and produce a virtual image at a viewing aperture. Electronics are associated with the array to produce real images in accordance with messages received by the receiver. The display is sufficiently small to mount in a hand held microphone for viewing by the operator while using the microphone.

Abstract: A field emission device (100, 150) includes a cathode plate (102, 180) having electron emitters (116), an anode plate (104, 170) having a phosphor (107, 207, 307, 407) activated by electrons (119) emitted by electron emitters (116), and a vacuum bridge focusing structure (118, 158, 218, 318) for focusing electrons (119) emitted by electron emitters (116). Vacuum bridge focusing structure (118, 158, 218, 318) has landings (121, 122, 221, 322), which are attached to cathode plate (102, 180), and further has bridges (120, 220, 320), which extend above and beyond landings (121, 122, 221, 322, 421) to provide a self-supporting structure that is spaced apart from cathode plate (102, 180).

Abstract: A field emission device (400) includes a plastically-deformable, ceramic, stamped substrate (200) made from a plastically deformable ceramic, which in the preferred embodiment includes a calendered tape. The plastically-deformable, ceramic, stamped substrate (200) includes first and second opposed surfaces (202, 204) and defines apertures (206) in which are formed extraction electrodes (410). The field emission device (400) further includes an electron-emissive layer (418) being formed on the first opposed surface (202). Cathodes (420) are disposed on the electron-emissive layer (418) and cross the extraction electrodes (410) at an angle of 90.degree.. A method for fabricating said field emission device (400) includes stamping a layer (100) of the softened calendered tape with a die (300) to define the apertures (206) and grooves (208, 212, 214).

Abstract: A method for affixing spacers (126, 226, 326) in a field emission display (100, 200, 300) includes the steps of: (i) providing a first display plate; providing a plurality of spacers (126, 226, 326) having first (128, 228, 328) and second opposed edges (130, 230, 330), (ii) coating first opposed edge (128, 228, 338) with a bonding layer (132, 232, 332), (iii) forming a metallic bonding pad (134, 234) on an inner surface (106, 206, 306) of first display plate, and (iv) applying a energy beam (136, 236, 336) to the bonding layer (132, 232, 332) and metallic bonding pad (134, 234), thereby forming a metallic bond.

Abstract: A field emission display (100) includes a cathode plate (110) having a plurality of electron emitters (114), an anode plate (122) having an anode (124) connected to a potential source (126), and an anode voltage pull-down circuit (127) having an input (106) and an output (104). Output (104) is connected to anode (124), and input (106) is connected to potential source (126). Preferably, anode voltage pull-down circuit (127) causes an anode voltage (120) at anode (124) to drop to about ground potential prior to generation of a discharge current by electron emitters (114) for neutralizing positively electrostatically charged surfaces (137, 138) within field emission display (100).

Abstract: A light emitting diode display package and method of fabricating a light emitting diode (LED) display package including a LED array display chip, fabricated of an array of LEDs, formed on a substrate, having connection pads positioned about the perimeter of the LED array display chip, a separate silicon driver chip having connection pads routed to an uppermost surface, positioned to cooperatively engage those of the display chip when properly registered and interconnected using wafer level processing technology. The display chip being flip chip mounted to the driver chip and having a layer of interchip bonding dielectric positioned between the space defined by the display chip and the driver chip. The LED display and driver chip package subsequently having selectively removed the substrate onto which the LED array was initially formed, thereby exposing the connection pads of the display chip and a remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer.

Abstract: A method for fabricating an array (300) of edge electron emitters (530) includes the steps of: forming first and second grooves (310, 320) in first and second opposing planar surfaces (101, 102), respectively, of a supporting substrate (110) to form an array of openings (330) therethrough; forming a dielectric layer (122) on the first planar surface (101) and an emission structure (120) on the dielectric layer (122); forming a plurality of cathodes (132) on the emission structure (120); forming gates (515) on a portion of the surfaces defining the first grooves (310); forming a masking film (710) on the cathodes (132)/emission structure (120); removing an outer, radial portion (726) of the masking film (710); etching the emission structure (120), the retracted masking film (710) forming a mask, thereby providing a predetermined configuration of the edge electron emitters (530) with respect to the gates (515) and cathodes (132).

Abstract: A method for affixing a plurality of spacers (102) within a field emission display (160) is disclosed. The method includes the steps of: (i) providing a plurality of members (104), (ii) coating an edge (106) of each of the plurality of members (104) with a metal to provide a bonding layer (108), (iii) forming a metallic bonding pad (132) on the inner surface of an anode (120) to provide a modified anode (130), (iv) affixing a plurality of metallic compliant members (112) to the bonding layer (108) by using ball bonding techniques, and (v) affixing the metallic compliant members (112) to the metallic bonding pad (132), while positioning the spacer (102) perpendicularly with respect to the modified anode (130), by using thermocompression metal bonding techniques.