Abstract: Described herein in various embodiments are techniques to better coordinate long wakeup events on a network processor that are due to radio or network activity with the long wakeups that are due to requests from an application processor. In one embodiment, power management logic can receive wake requests from system processes upon notice that one or more application processors are transitioning into a low power state. The power management logic can coalesce the wake requests based on a supplied margin and determine a wake timeframe in which the application processor may be opportunistically woken from the low power state. The power management logic can provide the wake timeframe for the application processor to a network processor in the system. The network processor can opportunistically cause an early wake of the application processor during the wake timeframe.

Abstract: An example computer-implemented method includes determining, by an electronic device, that the electronic device has not received a user activity for an interval of time. The method also includes determining, by the electronic device, a contextual state of the electronic device, and adapting, by the electronic device, a sleep delay value based on the determined contextual state of the electronic device. The method also includes determining that the interval of time has exceeded the sleep delay value, and responsive to determining that the interval of time has exceeded the sleep delay value, transitioning, by the electronic device, from a first power state to a second power state, where the first power state is higher or lower than the second power state.

Abstract: In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.

Abstract: Embodiments provide for a computer implemented method comprising sampling one or more power and performance metrics of a processor; determining an energy cost per instruction based on the one or more power and performance metrics; determining an efficiency metric based on the energy cost per instruction; computing an efficiency control error based on a difference between a current efficiency metric and a target efficiency metric; setting an efficiency control effort based on the efficiency control error; determining a performance control effort, the performance control effort determined by a performance controller for the processor; and adjusting the performance control effort based on the efficiency control effort, wherein adjusting the performance control effort reduces power consumption of the processor.

Abstract: In some implementations, a user device can schedule tasks based on user behavior. For example, the user device can receive a task request that includes a time window and user/device context parameters for performing the task. The user device can predict a time when the user/device context is optimal for performing the task during the time window based on historical context data. For example, the user device can generate an optimal context score for the task based on the context parameters and the historical context data. The user device can execute the requested task at a current time within the time window when a context score for the current context exceeds a threshold determined based on the optimal context score.

Abstract: Examples of the disclosure are directed to methods of managing power of various modules of an electronic device to prevent the voltage of the battery from falling to an undervoltage lockout (UVLO) threshold. In some examples, software operating on the electronic device or an associated electronic device (e.g., a paired electronic device) may assign power budgets to one or more modules, thereby preventing each module from drawing its maximum current capacity and causing the battery's voltage level to fall to the UVLO threshold. In some examples, a pre-UVLO threshold (i.e., a threshold higher than the UVLO threshold) may be used to modify the states of one or more modules to save power as the voltage of the battery approaches the UVLO threshold, but before the device must be fully powered off.

Abstract: An apparatus for determining an average current through an inductor of a regulator circuit is disclosed. A counter unit may be configured to receive a control signal, which includes a plurality of pulses, from a Power Management Unit (PMU), and determine a number of pulses received during a predetermined period of time. A pulse sampler unit may determine a duration of a given pulse of the plurality of pulses. Circuitry may be configured to determine the average current through the inductor during the predetermined period of time dependent upon the number of pulses received during the predetermined period of time and the duration of the given pulse.

Abstract: In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.

Abstract: Embodiments of a computing system that may monitor energy usage are disclosed. The embodiments may provide a low overhead method for determining energy usage of a given application or process. Circuitry is configured to determine a respective energy for each of the plurality of operations and sum each respective energy for at least some of the plurality of operations to generate a normalized total. The circuitry may be further configured to scale the normalized total to generate an energy value, and store the energy value in a register. System software may then read the energy value from the register and determine an energy usage for at least one application dependent upon the energy value.

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

Abstract: Examples of the disclosure are directed to methods of managing power of various modules of an electronic device to prevent the voltage of the battery from falling to an undervoltage lockout (UVLO) threshold. In some examples, software operating on the electronic device or an associated electronic device (e.g., a paired electronic device) may assign power budgets to one or more modules, thereby preventing each module from drawing its maximum current capacity and causing the battery's voltage level to fall to the UVLO threshold. In some examples, a pre-UVLO threshold (i.e., a threshold higher than the UVLO threshold) may be used to modify the states of one or more modules to save power as the voltage of the battery approaches the UVLO threshold, but before the device must be fully powered off.

Abstract: An apparatus for determining an average current through an inductor of a regulator circuit is disclosed. A counter unit may be configured to receive a control signal, which includes a plurality of pulses, from a Power Management Unit (PMU), and determine a number of pulses received during a predetermined period of time. A pulse sampler unit may determine a duration of a given pulse of the plurality of pulses. Circuitry may be configured to determine the average current through the inductor during the predetermined period of time dependent upon the number of pulses received during the predetermined period of time and the duration of the given pulse.

Abstract: A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.

Abstract: Described herein in various embodiments are techniques to better coordinate long wakeup events on a network processor that are due to radio or network activity with the long wakeups that are due to requests from an application processor. In one embodiment, power management logic can receive wake requests from system processes upon notice that one or more application processors are transitioning into a low power state. The power management logic can coalesce the wake requests based on a supplied margin and determine a wake timeframe in which the application processor may be opportunistically woken from the low power state. The power management logic can provide the wake timeframe for the application processor to a network processor in the system. The network processor can opportunistically cause an early wake of the application processor during the wake timeframe.

Abstract: An example computer-implemented method includes determining, by an electronic device, that the electronic device has not received a user activity for an interval of time. The method also includes determining, by the electronic device, a contextual state of the electronic device, and adapting, by the electronic device, a sleep delay value based on the determined contextual state of the electronic device. The method also includes determining that the interval of time has exceeded the sleep delay value, and responsive to determining that the interval of time has exceeded the sleep delay value, transitioning, by the electronic device, from a first power state to a second power state, where the first power state is higher or lower than the second power state.

Abstract: Systems and methods are disclosed for advising a user when an energy storage device in a computing system needs charging. State of charge data of the energy storage device can be measured and stored at regular intervals. The historic state of charge data can be queried over a plurality of intervals and a state of charge curve generated that is representative of a user's charging habits over time. The state of charge curve can be used to generate a rate of charge histogram and an acceleration of charge histogram. These can be used to predict when a user will charge next, and whether the energy storage device will have an amount of energy below a predetermined threshold amount before the next predicted charging time. A first device can determine when a second device typically charges and whether the energy storage device in the second device will have an amount of energy below the predetermined threshold amount before the next predicted charge time for the second device.

Abstract: A method and apparatus to alter acoustic noise induced by processor performance changes is disclosed. In one embodiment, a processor having one or more processor cores may execute instructions of one or more applications. The performance level (e.g., supply voltage and/or clock frequency) may be adjusted in accordance with workload demands. One or more of the applications executing on a core of the processor may exhibit periodic behavior, thereby causing periodic changes (e.g., increases) in the performance level. Performance monitoring may be conducted and may detect the periodic changes in the workload of the application. Responsive to the detection of the periodic changes, a power management unit may subsequently cause future performance level changes associated with the application to occur aperiodically.

Abstract: The embodiments set forth a technique for targeted scaling of the voltage and/or frequency of hardware components included in a mobile computing device. One embodiment involves independently analyzing the individual frame rates of each animation within a user interface (UI) of a mobile computing device instead of analyzing the frame rate of the UI as a whole. This can involve establishing, for each animation being displayed within the UI, a corresponding performance control pipeline that generates a control signal for scaling a performance mode of the hardware components (e.g., a Central Processing Unit (CPU)) included in the mobile computing device. In this manner, the control signals generated by the performance control pipelines can be aggregated to produce a control signal that causes a power management component to scale the performance mode(s) of the hardware components.

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.