Abstract: The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

Abstract: A microactuator, for example for a disc drive, comprising a substrate, a sandwich structure on the substrate, and a passivation layer over the substrate and the sandwich structure. The sandwich structure has a bottom electrode formed from noble metal, a piezoelectric layer, and a top electrode formed from noble metal. The microactuator further has one or both of a bottom adhesion layer present between the bottom electrode and the passivation layer, and a top adhesion layer present between the top electrode and the passivation layer. That is, the microactuator may have only the bottom adhesion layer, only the top adhesion layer, or both the bottom adhesion layer and the top adhesion layer.

Abstract: An RF asset tracking device for cargo containers that has an extended operational life, due to a power management system and multiple power sources. The device has a solar cell and high capacity supercapacitor as a principal power source and a rechargeable battery as an auxiliary power source. Control circuitries manage and regulate the usage of the primary and secondary sources. Together, these power sources provide sufficient power for the tracking device to operate for an extended period of time, thus increasing the period between needed maintenance and decreasing downtime and thus cost.

Abstract: Vibration of a transducer slider can be used during slider fly height calibration to detect contact of the transducer slider with a disc surface. Amplification of the vibration may cause the transducer slider to tap the disc surface rather than drag across the disc surface when detecting contact with the disc surface. Amplification may be achieved by applying an in-phase AC signal to the transducer slider at the same frequency as the vibration of the slider. Reduced contact between the slider and the disc surface reduces wear on and the possibility of damage to the transducer slider and/or the disc surface. Once the fly height of the transducer slider is calibrated, the AC signal may be shifted out-of-phase with the slider vibration to dampen the slider vibration.

Abstract: A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed.

Abstract: A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value.

Abstract: A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

Abstract: A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.

Abstract: A wafer is formed having a plurality of laser-to-slider submount features on a first surface. An etching process is used to form scribe lines between the submounts on the first surface of the wafer. The wafer is separated at the scribe lines to form the submounts.

Abstract: A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed.

Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode.

Abstract: A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed.

Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal.

Abstract: Vibration of a transducer slider can be used during slider fly height calibration to detect contact of the transducer slider with a disc surface. Amplification of the vibration may cause the transducer slider to tap the disc surface rather than drag across the disc surface when detecting contact with the disc surface. Amplification may be achieved by applying an in-phase AC signal to the transducer slider at the same frequency as the vibration of the slider. Reduced contact between the slider and the disc surface reduces wear on and the possibility of damage to the transducer slider and/or the disc surface. Once the fly height of the transducer slider is calibrated, the AC signal may be shifted out-of-phase with the slider vibration to dampen the slider vibration.

Abstract: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N?1 output lines.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.

Abstract: Apparatus and method for forming a head gimbal assembly (HGA). In accordance with various embodiments, a slider is formed with opposing first and second side surfaces, an air bearing feature on said first side surface and a dimple extending from said second side surface adapted to facilitate multi-axial rotation of the slider.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.