Abstract: Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies.

Abstract: A supported probe device that has a probe tip and probe body, the probe body having a sample facing surface and an opposing surface. The probe tip and a first electrode are on the sample facing surface. A second electrode is present on the probe body opposing surface. A third electrode is spaced from the second electrode, so that the second electrode is between the third electrode and the probe body. A first DC voltage source is electrically coupled to the first electrode, as is a first sensing circuit. A second DC voltage source is electrically coupled to the second electrode, and an AC voltage source electrically coupled to the third electrode. The probe body may be cantilevered.

Abstract: Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

Abstract: A shielded integrated circuit structure including an integrated circuit having a plurality of functional elements thereon, and a tiled array comprising a plurality of shielding elements, each functional element having one of the plurality of shielding elements proximate thereto. The shielding elements comprise a magnetic material having a saturation less than or equal to 20,000 gauss.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.

Abstract: A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed.

Abstract: A fluid dynamic bearing formed by a microelectromechanical systems (MEMS) wafer-level batch-fabrication process is provided. The process results in a high performance and high reliability fluid dynamic bearing having features including higher bearing lifetime at high RPM, improved bearing stiffness, durability and thrust/restoring forces capabilities. The present invention is especially useful with small form factor disc drive memory devices having constraints in motor height, such as a 2.5 inch disc drive, requiring high performance including high rotational speed and large areal density. A sacrificial layer is utilized in the process to simultaneously form symmetrical facing surfaces of relatively rotatable components. The facing surfaces define, therebetween, a desired feature, such as a journal bearing, a thrust bearing, a fluid channel, a fluid reservoir, a capillary seal, pressure generating grooves, and other profile geometries.

Abstract: Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.

Abstract: Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode.

Abstract: An integrated circuit chip having a heat spreader comprising CVD diamond extending along the chip support body and thermal vias extending through the support body in regions free of active devices or functional elements. The thermal vias may thermally conductive and electrically conductive or may be thermally conductive and electrically resistive. The integrated circuit chips may be 3D integrated circuit chips.

Abstract: A micro magnetic device having a body defining at least part of an enclosed chamber, the body comprising a first sidewall and a second sidewall. A pole comprising a soft magnetic material is within the chamber and an electrically conductive coil is positioned around the pole. A diaphragm is connected to the first sidewall and a permanent dipole magnet is connected to the second sidewall at a first end and to the diaphragm at a second end. The dipole magnet is offset centrally from the pole. The diaphragm may also be offset centrally from the first pole. The micro magnetic device may be made by MEMS or thin film techniques.

Abstract: A method and apparatus for managing data, particularly in regard to non-volatile memory cells. In some embodiments, at least two actuating conductors are at least partially surrounded by a main ferromagnetic core and an adjacent hard magnet. When current is conducted through the actuating conductors, a flexible beam is induced to traverse a first air gap that defines a high resistance position and a low resistance position.

Abstract: A probe system that has a probe body comprising at least three arms extending from a central region and a probe tip centrally located on the probe body in the central region. A substrate is proximate the probe body opposite the probe tip. A first electrode is positioned to provide a centrally positioned voltage across the probe body and the substrate and a second electrode set is positioned radially outward from the first electrode, to provide an outer voltage across at least one of the at least three arms and the substrate. The probe structure may have, for example, four arms. Methods of actuating the probe tip are provided.

Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode.

Abstract: Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies.

Abstract: A micro magnetic device with a micro magnetic speaker unit having a first element, a second element, and a membrane therebetween. Each of the elements comprises a body, a pole of soft magnetic material, an electrically conductive coil positioned around the pole, and a permanent magnet connected to the membrane. The first element and the second element are magnetically identical. A plurality of speaker units can be combined to provide a speaker array.

Abstract: Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.

Abstract: A memory array and a method for accessing a memory array including: receiving an address from a host related to relevant data; accessing a first module based on the address received from the host, wherein accessing the first module includes: decoding the address for the first module; enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module; and outputting information regarding the first module; and accessing a second module based on the address received from the host, wherein accessing the second module includes: decoding the address for the second module; enabling a wordline based on the decoded address for the second module and sensing the contents of one or more bits at the decoded address for the second module; and outputting information regarding the second module, wherein the step of decoding the address for the second module occurs while the step of enabling a wordline based on the decoded address for