Abstract: Herein disclosed is an upgradable SMART (Self-Monitoring Analysis and Reporting Technology) battery pack which is capable of upgrading a SMART function thereof. The upgradable SMART battery pack comprises a battery array, a host interface for supplying power to a host and performing a SMART communication therewith, a protection circuit for protecting battery cells in the battery array from overcurrent or overvoltage, a microprocessor for monitoring a current state of the battery array, calculating a battery capacity thereof and controlling the SMART communication with the host via the host interface, a nonvolatile memory for storing a program necessary to an operation of the microprocessor and unique battery information, and a signal processor for converting a level of a signal to be sent to the host via the host interface into that desired by the host and processing the level-converted signal.

Abstract: A method of fabricating a liquid crystal display device includes: providing first and second substrates having a plurality of unit cell regions; forming a plurality of main seal patterns on the first substrate, each main seal pattern having an injection; forming an auxiliary seal pattern on the first substrate, the auxiliary seal pattern surrounding the plurality of main seal patterns and having at least one open portion; attaching the first substrate to the second substrate; providing an adhesive at the at least one open portion; and etching the first and second substrates, wherein a viscosity of the adhesive is within a range of about 5 to 100 centipoises (cP).

Abstract: A complementary clock generator and a method for generating complementary clocks are disclosed. A complementary clock generator according to the present invention includes a first inverter, a first transmitting switch and a second transmitting switch. The first inverter outputs inverted clock signals by inverting input clock signals. The first transmitting switch has an input terminal, an output terminal, a first control input terminal and a second control input terminal, and connects the input terminal to the output terminal when the input clock signal reaches the first control input terminal and the inverted clock signal from the first inverter reaches the second control input terminal.

Abstract: A pulse generating circuit for a dynamic random access memory includes a fixed pulse generating unit receiving an input signal and generating an output pulse signal of a fixed width, a pulse delay unit receiving the input signal and delaying an output pulse signal of a variable width, a pulse width detecting unit receiving the input signal and an inverted input signa, outputting a first flag signal displaying a low pulse width by detecting the low pulse width of the input signal, and outputting a second flag signal displaying a high pulse width by detecting the high pulse width of the input signal, a NOR gate performing a logical operation on the first flag signal and the second flag signal and outputting a third flag signal, and a multiplexer coupled to the fixed pulse generating unit, the pulse delay unit, and the pulse width detecting unit and outputting an output pulse signal in accordance with the third flag signal.

Abstract: An improved substrate voltage (VBB) generation circuit is disclosed. The circuit reduces variations in VBB (.DELTA.VBB) caused by variations (.DELTA.VCC) in a system voltage (VCC) by making a threshold voltage (Vt) of a logic element, e.g., an inverter of in a buffer, more sensitive to .DELTA.VCC. In contrast, the conventional art had attempted to reduce .DELTA.VBB by making the Vt of the logic element less sensitive to .DELTA.VCC. Two features of the improved logic element of the circuit contribute to the reduction of .DELTA.VBB. These features are: adopting an opposite channel ratio arrangement versus the conventional art; and incorporating additional active resistors.

Abstract: A memory device and method are provided that permits repair a predetermined normal word line by a redundant word line in an identical bank, for example, in a multi-bank device. Each bank of the memory device includes a single memory block of a plurality of memory blocks having redundant word lines. A refresh operation can be performed in each banks by simultaneously driving normal word lines and the redundant word lines when each the memory blocks are accessed with the exception of the single memory block including the redundant word lines.

Abstract: A wordline driver for use with a SDRAM of a semiconductor device is provided. The wordline driver can be used for a global wordline driver suitable for a merged bank architecture (MBA). The wordline driver can include a set unit for setting a wordline driver by receiving coding signals coded in an X-address predecoder. A reset unit resets the wordline driver in accordance with a reset signal controlled by a precharge command and a first coding signal. A drive unit enables/disables a wordline in accordance with operations of the set and reset units, and a latch unit latches an enabled/disabled state of the wordline. The coding signal can include upper, intermediate and lower coding signals based on a multi-bit X-address. Accordingly, the present invention is effective for the MBA in which the X-address predecoder is shared by providing a latch in a global wordline itself and latching an enabled/disabled state of the global wordline.

Abstract: An improved current detection start-up circuit for a reference voltage circuit which restarts a reference voltage circuit when a reference voltage drops by a predetermined level, i.e., turns off, due to noise or a variation of a system voltage. The circuit includes: a current detection circuit for detecting the current being applied to a reference voltage circuit; and a start-up circuit for starting the reference voltage circuit when the current detected by the current detection circuit is below a predetermined level.

Abstract: A digital delay locked loop (DLL) includes a phase detector for outputting a comparing signal by comparing a system clock signal with a chip clock signal, a shift register for sequentially shifting data bit values in both the directions in accordance with the comparing signal, a phase delay unit for delaying and outputting the system clock signal in accordance with each bit value of the shift register, a domain selecting controller for detecting an overflow or an underflow condition of the shift register and outputting a domain selection controlling signal, and a domain selector for adjusting the phase of a driving signal from one region comprising 0.degree..about.180.degree. and to another area comprising 180.degree..about.360.degree. and carrying out a domain transition whenever an overflow or an underflow condition is generated when the phase reaches a boundary region of the two domains.

Abstract: A complementary clock generator and a method for generating complementary clocks are disclosed. A complementary clock generator according to the present invention includes a first inverter, a first transmitting switch and a second transmitting switch. The first inverter outputs inverted clock signals by inverting input clock signals. The first transmitting switch has an input terminal, an output terminal, a first control input terminal and a second control input terminal, and connects the input terminal to the output terminal when the input clock signal reaches the first control input terminal and the inverted clock signal from the first inverter reaches the second control input terminal.

Abstract: A circuit for detecting leakage voltage of a MOS capacitor, the detecting circuit including a timing control signal generator for generating a timing control signal; a sample/hold circuit for sampling and holding a first voltage, the sample/hold circuit comprising a switching circuit switched by an output of the timing control signal generator and being operatively coupled to a MOS capacitor; a monitoring capacitor for monitoring a leakage voltage of the MOS capacitor operatively coupled to the sample/hold circuit; a monitoring capacitor precharge circuit for holding a second voltage in the monitoring capacitor; and a leakage voltage detecting portion for detecting when a leakage voltage of the monitoring capacitor is below a predetermined value. The leakage voltage detecting portion is also capable of detecting what value the leakage voltage of the monitoring capacitor is, for example, when the leakage voltage is below the predetermined value.

Abstract: An improved delay characteristic compensation circuit for a memory device which is capable of constantly maintaining the characteristic of the delay path by connecting or disconnecting the delay devices to the delay path by detecting quickly the variation of the supply voltage, which includes a signal delay unit for sequentially delaying an input signal; a voltage variation detector for detecting a variation of a digital supply voltage and adjusting the level of a divide voltage with respect to the supply voltage at a predetermined ratio; a code data generator for generating a code data in accordance with the voltage adjusted by the voltage variation detector; and a delay characteristic compensation unit for connecting a predetermined number of delay devices to a delay path of the delay unit in accordance with a code data generated by the code data generator for dividing the same so as to constantly maintain the delay characteristic of the delay unit.