Patents by Inventor Daisuke Matsushita
Daisuke Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240155774Abstract: A wiring transfer plate for forming wiring to be transferred to another component includes: a base; a plating base material layer formed as a release layer on the base; an insulating layer covering the base with an opening above the plating base material layer; and a projecting structure formed on the insulating layer for forming, in an insulating layer of a component to which the wiring is to be transferred, a via hole for a via electrode.Type: ApplicationFiled: March 16, 2022Publication date: May 9, 2024Inventors: Takayoshi NIRENGI, Akihiro OISHI, Tsutomu AISAKA, Daisuke MATSUSHITA, Jumpei IWANAGA, Tadashi TOJO
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Publication number: 20240153859Abstract: A wiring body disposed above a substrate including a conductor includes: a via electrode provided in a via hole formed in an insulating layer above the substrate and connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. The material or structure of a lower layer in the via electrode and the material or structure of a lower layer in the wiring are different.Type: ApplicationFiled: March 16, 2022Publication date: May 9, 2024Inventors: Takayoshi NIRENGI, Akihiro OISHI, Tsutomu AISAKA, Daisuke MATSUSHITA, Jumpei IWANAGA, Tadashi TOJO
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Publication number: 20240147617Abstract: A wiring body disposed above a substrate including a conductor including: a via electrode provided in a via hole formed in an insulating layer above the substrate and connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. A lower layer included in the via electrode and located above the insulating layer and a lower layer included in the wiring include the same material.Type: ApplicationFiled: March 16, 2022Publication date: May 2, 2024Inventors: Takayoshi NIRENGI, Akihiro OISHI, Tsutomu AISAKA, Daisuke MATSUSHITA, Jumpei IWANAGA, Tadashi TOJO
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Publication number: 20240145374Abstract: A wiring body disposed above a substrate including a conductor includes: a via electrode provided in a via hole formed in an insulating layer above the substrate and connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. The via electrode includes: a seed layer formed along an inner surface of the insulating layer from above the conductor in the via hole; a via electrode body layer formed to be located above the seed layer and fill the via hole; and an adhesion layer formed between the seed layer and the inner surface of the insulating layer in the via hole.Type: ApplicationFiled: March 16, 2022Publication date: May 2, 2024Inventors: Takayoshi NIRENGI, Akihiro OISHI, Tsutomu AISAKA, Daisuke MATSUSHITA, Jumpei IWANAGA, Tadashi TOJO
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Patent number: 11956146Abstract: A reception unit (210) receives an addition requesting frame for requesting addition of a new flow. A first search unit (241) performs, using a network-information database (280), a first search for searching for a schedule and a path assignable to the new flow without the schedule and the path of each existing flow being changed, when the addition requesting frame is received. A second search unit (242) performs a second search for changing the schedule and the path of each existing flow and searching for the schedule and the path assignable to the new flow, using the network-information database, when the schedule and the path assignable to the new flow have not been found by the first search. A response unit (260) transmits an addition responding frame.Type: GrantFiled: July 20, 2022Date of Patent: April 9, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Makoto Kubomi, Ryuma Matsushita, Daisuke Takita, Yoshifumi Hotta
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Patent number: 11947304Abstract: A cleaning device includes: a cleaning brush that has bristles that rotate and contact a surface, to which toner has adhered, of a cleaning member to be cleaned, the cleaning brush removing the toner adhered to the surface of the cleaning member; a first contact member that contacts the bristles without a position of the first contact member relative to a position of the cleaning brush being changed; and a second contact member that contacts the bristles at a location downstream from the first contact member in a direction of rotation of the cleaning brush and without a position of the second contact member relative to the position of the cleaning brush being changed, and that is disposed on an extension line extended from a line between an axial center of the cleaning brush and a base of the bristles that move away from the first contact member.Type: GrantFiled: September 20, 2022Date of Patent: April 2, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Haruyuki Ideura, Daisuke Tanaka, Takeshi Yasuda, Kaoru Matsushita
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Patent number: 11945923Abstract: Disclosed is a method for producing an electrolytic capacitor, the method including the steps of preparing an anode foil that includes a dielectric layer, a cathode foil, and a fiber structure; preparing a conductive polymer dispersion liquid that contains a conductive polymer component and a dispersion medium; producing a separator by applying the conductive polymer dispersion liquid to the fiber structure and then removing at least a portion of the dispersion medium; and producing a capacitor element by sequentially stacking the anode foil, the separator, and the cathode foil. The dispersion medium contains water. The fiber structure contains a synthetic fiber in an amount of 50 mass % or more. The fiber structure has a density of 0.2 g/cm3 or more and less than 0.45 g/cm3.Type: GrantFiled: January 29, 2020Date of Patent: April 2, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Daisuke Kubo, Hiroyuki Arima, Tomoyuki Tashiro, Kazuhiro Takatani, Kenta Chashiro, Shumpei Matsushita
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Patent number: 10631450Abstract: A component mounting system reduces the waste of components while mounting components via an application material. The system determines whether or not to permit the start of the mounting process to a plurality of applying locations based on the post-application elapsed time that has elapsed after the application of the adhesive to the applying location. That is, the system predicts the post-application elapsed time exceeds the time limit at the mounting timing at which the component is mounted in the mounting process for each applying location. If the plurality of applying locations include no applying location where the post-application elapsed time exceeds the time limit at the mounting timing, the start of the mounting process is permitted. However, if there is any applying location where the post-application elapsed time exceeds the time limit at the mounting timing, the start of the mounting process is prohibited.Type: GrantFiled: July 10, 2015Date of Patent: April 21, 2020Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Daisuke Matsushita, Daisuke Kasuga
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Publication number: 20200066748Abstract: According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of insulating layers and a plurality of conductive layers are alternately stacked above a substrate, a pillar that penetrates the stacked body while extending in a stacking direction of the stacked body, and a semiconductor layer, a first insulating layer, a charge accumulation layer, and a second insulating layer, which are stacked on a side surface of the pillar in order from the pillar, wherein the semiconductor layer has an average grain size that is larger on a side nearer to the pillar and is smaller on a side nearer to the first insulating layer.Type: ApplicationFiled: December 4, 2018Publication date: February 27, 2020Applicant: Toshiba Memory CorporationInventors: Daisuke MATSUSHITA, Yui KAGI, Tatsuya FUJISHIMA, Masayuki SHISHIDO, Nozomi KIDO, Tomonori KAJINO, Nobuhito KUGE
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Publication number: 20180199476Abstract: A component mounting system reduces the waste of components while mounting components via an application material. The system determines whether or not to permit the start of the mounting process to a plurality of applying locations based on the post-application elapsed time that has elapsed after the application of the adhesive to the applying location. That is, the system predicts the post-application elapsed time exceeds the time limit at the mounting timing at which the component is mounted in the mounting process for each applying location. If the plurality of applying locations include no applying location where the post-application elapsed time exceeds the time limit at the mounting timing, the start of the mounting process is permitted. However, if there is any applying location where the post-application elapsed time exceeds the time limit at the mounting timing, the start of the mounting process is prohibited.Type: ApplicationFiled: July 10, 2015Publication date: July 12, 2018Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Daisuke MATSUSHITA, Daisuke KASUGA
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Patent number: 9966736Abstract: A spark plug having a center electrode, a ground electrode, and a noble metal tip that is joined to a part of the ground electrode near one end of the ground electrode via a fused portion. The fused portion extends outward beyond an outer shape of the noble metal tip so that a part of the fused portion is present at each of positions that are located inward from and separated from both side edges of the ground electrode in a width direction of the ground electrode. The fused portion includes a fused protrusion that is located near at least one of two side edges of the noble metal tip in the width direction of the ground electrode and that protrudes in a direction away from the one end of the ground electrode.Type: GrantFiled: April 7, 2017Date of Patent: May 8, 2018Assignee: NGK SPARK PLUG CO., LTD.Inventors: Daisuke Matsushita, Masahiro Inoue
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Patent number: 9935122Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.Type: GrantFiled: March 16, 2016Date of Patent: April 3, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsunehiro Ino, Daisuke Matsushita, Yasushi Nakasaki, Misako Morota, Akira Takashima, Kenichiro Toratani
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Patent number: 9928908Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.Type: GrantFiled: February 6, 2017Date of Patent: March 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Reika Ichihara, Daisuke Matsushita, Shosuke Fujii
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Patent number: 9865606Abstract: According to one embodiment, a semiconductor device includes a first region having a first conductivity type in a semiconductor region; a second region having a second conductivity type in the semiconductor region; a gate electrode above a first part of the semiconductor region between the first region and the second region; a gate insulating layer between the first part and the gate electrode; a third region having the first conductivity type below the second region; and a fourth region across the second region and the third region and including a first impurity.Type: GrantFiled: March 7, 2016Date of Patent: January 9, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Chika Tanaka, Daisuke Matsushita
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Publication number: 20170294763Abstract: A spark plug having a center electrode, a ground electrode, and a noble metal tip that is joined to a part of the ground electrode near one end of the ground electrode via a fused portion. The fused portion extends outward beyond an outer shape of the noble metal tip so that a part of the fused portion is present at each of positions that are located inward from and separated from both side edges of the ground electrode in a width direction of the ground electrode. The fused portion includes a fused protrusion that is located near at least one of two side edges of the noble metal tip in the width direction of the ground electrode and that protrudes in a direction away from the one end of the ground electrode.Type: ApplicationFiled: April 7, 2017Publication date: October 12, 2017Applicant: NGK SPARK PLUG CO., LTD.Inventors: Daisuke MATSUSHITA, Masahiro INOUE
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Patent number: 9780170Abstract: A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.Type: GrantFiled: July 7, 2016Date of Patent: October 3, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kensuke Ota, Toshifumi Irisawa, Tomoya Kawai, Daisuke Matsushita, Tsutomu Tezuka
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Publication number: 20170271466Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage layer. The first oxide layer is provided between the semiconductor layer and the first electrode. The second oxide layer is provided between the first oxide layer and the first electrode. The storage layer is provided between the first and second oxide layers. The storage layer includes a first region including silicon nitride, a second region provided between the first region and the second oxide layer and including silicon nitride, and a third region provided between the first and second regions. The third region includes a plurality of first metal atoms. A first density of bond of the first metal atoms in the third region is lower than a second density of bond of the first metal atom and a nitrogen atom in the third region.Type: ApplicationFiled: September 15, 2016Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daisuke MATSUSHITA, Yasushi NAKASAKI, Tsunehiro INO
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Patent number: 9768265Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage layer. The first oxide layer is provided between the semiconductor layer and the first electrode. The second oxide layer is provided between the first oxide layer and the first electrode. The storage layer is provided between the first and second oxide layers. The storage layer includes a first region including silicon nitride, a second region provided between the first region and the second oxide layer and including silicon nitride, and a third region provided between the first and second regions. The third region includes a plurality of first metal atoms. A first density of bond of the first metal atoms in the third region is lower than a second density of bond of the first metal atom and a nitrogen atom in the third region.Type: GrantFiled: September 15, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Daisuke Matsushita, Yasushi Nakasaki, Tsunehiro Ino
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Patent number: 9728881Abstract: A connector terminal includes first and second arm parts, an interconnection part, a first contactor formed of a piece of sheet which is in a bent shape so as to have the first end laid over on a second end of the sheet with reference to a bent part that is an opposite side to a side where the first end of the sheet and the second end thereof are present, and a second contactor formed of a piece of sheet which is in a bent shape so as to have the first end laid over on a second end of the sheet with reference to a bent part that is an opposite side to a side where the first end of the sheet and the second end thereof are located, and the second contactor facing the first contactor.Type: GrantFiled: October 27, 2016Date of Patent: August 8, 2017Assignee: DAI-ICHI SEIKO CO., LTD.Inventors: Takayoshi Endo, Jun Mukunoki, Daisuke Matsushita
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Patent number: 9698236Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.Type: GrantFiled: March 8, 2016Date of Patent: July 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Yuuichiro Mitani