Patents by Inventor Daisuke Mizutani

Daisuke Mizutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11931630
    Abstract: A head includes a face portion, a sole portion, and an internal weight portion provided on an inner surface of the sole portion and located apart from the face portion. The internal weight portion includes a base portion, and a protruding portion protruding from the base portion toward a face side and located apart from the inner surface of the sole portion. The protruding portion is positioned on the face side with respect to the head center of gravity. A thickness of a toe-side part of the protruding portion and/or a thickness of a heel-side part of the protruding portion is greater than a thickness of a middle part of the protruding portion. Alternatively, a middle part of the protruding portion in a toe-heel direction is absent. The internal weight portion may be formed integrally with the sole portion, or may be a different member from the sole portion.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: March 19, 2024
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventors: Naruhiro Mizutani, Daisuke Kohno, Akio Yamamoto
  • Patent number: 11317520
    Abstract: A circuit board includes: an insulating layer; a capacitor which is provided in the insulating layer and which includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including an opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a recess part at a position corresponding to the opening part; and a conductor via provided in the insulating layer, penetrating the dielectric layer, the opening part and the recess part, being in contact with the recess part, and being smaller than the opening part in plan view.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 26, 2022
    Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki Akahoshi, Masateru Koide, Manabu Watanabe, Seigo Yamawaki, Kei Fukui
  • Patent number: 11057996
    Abstract: A circuit board includes: a first substrate including a first through hole, a first metal layer formed over an inner wall of the first through hole, and a first conductive composite resin provided on an inner side of the first metal layer of the first through hole; and a second substrate stacked together with the first substrate and including a second through hole that faces the first through hole and has a first open end which is provided on a side of the first through hole and is located on the inner side of the first metal layer, and a second conductive composite resin that is provided in the second through hole and is coupled to the first conductive composite resin.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: July 6, 2021
    Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Toshiki Iwai, Daisuke Mizutani, Seiki Sakuyama, Taiji Sakai
  • Patent number: 10896871
    Abstract: A circuit board includes an insulating layer; a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first and the second conductor vias.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Masaharu Furuyama, Daisuke Mizutani
  • Patent number: 10770386
    Abstract: A wiring board includes: an insulating layer that includes a first surface over which an electronic component is mounted and a second surface opposite to the first surface; a conductive layer that is disposed on the second surface; a via that is provided inside a first through-hole that penetrates a portion between the first surface and the second surface of the insulating layer; an electrode that is disposed on the first surface and connected to the via; and a glass plate that is not contact with the conductive layer and is disposed on the first surface and includes a second through-hole through which the electrode is disposed.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: September 8, 2020
    Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Toshiki Iwai, Daisuke Mizutani
  • Patent number: 10734316
    Abstract: A wiring board includes: an insulating layer that includes a first surface over which an electronic component is mounted and a second surface opposite to the first surface; a conductive layer that is disposed on the second surface; a via that is provided inside a first through-hole that penetrates a portion between the first surface and the second surface of the insulating layer; an electrode that is disposed on the first surface and connected to the via; and a glass plate that is not contact with the conductive layer and is disposed on the first surface and includes a second through-hole through which the electrode is disposed.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 4, 2020
    Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Toshiki Iwai, Daisuke Mizutani
  • Publication number: 20200245463
    Abstract: A capacitor-embedded substrate includes a first conductor layer that is a power-supply layer and divided into a first and second regions, a second conductor layer that is a ground layer, a dielectric layer between the first and second conductor layers, and a third conductor layer that is a power-supply layer and displaced from the dielectric layer along a thickness direction of the substrate, a first via by which the first region and the third conductor layer are coupled, the first via being not coupled to the second conductor layer, and a second via by which the second region and the third conductor layer are coupled, the second via being not coupled to the second conductor layer, wherein the third conductor layer includes a narrowed portion narrower than other portions in the third conductor layer, between a coupled portion to the first via and a coupled portion to the second via.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 30, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki AKAHOSHI, Daisuke Mizutani
  • Patent number: 10701808
    Abstract: A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 30, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Daisuke Mizutani
  • Publication number: 20190306982
    Abstract: A circuit board includes an insulator layer, an electronic component built into the insulator layer, a first via penetrating the insulator layer, a second via extending from one surface of the insulator layer and coupled to the electronic component, and a metal layer formed over the one surface of the insulator layer, wherein a via pad is formed over the second via, an opening is formed between the metal layer and a first via side of the via pad, and the opposite side of the via pad to the first via side is coupled to the metal layer.
    Type: Application
    Filed: February 8, 2019
    Publication date: October 3, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Hideaki Nagaoka, Tomoyuki AKAHOSHI, Daisuke Mizutani
  • Publication number: 20190306981
    Abstract: A circuit substrate includes a first insulating layer, a capacitor disposed over the first insulating layer, the capacitor including a dielectric layer, a first conductor layer disposed on a first face of the dielectric layer, and a second conductor layer disposed on a second face opposite to the first face of the dielectric layer and having an electric resistivity higher than that of the first conductor layer, a third conductor layer disposed on a surface of the second conductor layer, the third conductor layer having an electric resistivity lower than that of the second conductor layer, a second insulating layer covering the capacitor, and a conductor via disposed in the second insulating layer, the conductor via being coupled to a portion of the third conductor layer.
    Type: Application
    Filed: January 31, 2019
    Publication date: October 3, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki AKAHOSHI
  • Publication number: 20190289715
    Abstract: A circuit board includes: a first substrate including a first through hole, a first metal layer formed over an inner wall of the first through hole, and a first conductive composite resin provided on an inner side of the first metal layer of the first through hole; and a second substrate stacked together with the first substrate and including a second through hole that faces the first through hole and has a first open end which is provided on a side of the first through hole and is located on the inner side of the first metal layer, and a second conductive composite resin that is provided in the second through hole and is coupled to the first conductive composite resin.
    Type: Application
    Filed: June 4, 2019
    Publication date: September 19, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Toshiki Iwai, Daisuke Mizutani, Seiki Sakuyama, Taiji Sakai
  • Publication number: 20190289718
    Abstract: A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Daisuke Mizutani
  • Publication number: 20190287893
    Abstract: A wiring substrate includes, a base substrate, a film capacitor, a first through via and a second through via. The film capacitor includes a first conductive film disposed on a surface of the base substrate, a second conductive film, and a dielectric film disposed between the first conductive film and the second conductive film. The first through via disposed in the base substrate, penetrates the base substrate and the capacitor, is electrically coupled to the second conductive film, and is insulated from the first conductive film. The second through via disposed in the base substrate, penetrates the base substrate, is electrically coupled to the first conductive film, and is insulated from the second conductive film.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 19, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Daisuke Mizutani
  • Patent number: 10396020
    Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 27, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kei Fukui, Youichi Hoshikawa, Hiromitsu Kobayashi, Hidehiko Fujisaki, Seigo Yamawaki, Masateru Koide, Manabu Watanabe, Daisuke Mizutani, Tomoyuki Akahoshi
  • Patent number: 10362677
    Abstract: A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 23, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Daisuke Mizutani
  • Publication number: 20190215963
    Abstract: A circuit board includes a first capacitor that includes a first dielectric layer, a first conductor layer disposed on a first surface of the first dielectric layer, and a second conductor layer disposed on a second surface of the first dielectric layer opposite to the first surface, a first insulating layer that is bonded to the first surface side with a first adhesive layer and has a higher elastic modulus than the first adhesive layer, and a second insulating layer that is bonded to the second surface side with a second adhesive layer and has a higher elastic modulus than the second adhesive layer.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Hideaki Nagaoka, Daisuke Mizutani
  • Patent number: D873295
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Mizutani, Yasuhisa Kurata, Tatsushi Sawada, Hidematsu Hayashi, Taketoshi Saito, Tomoharu Aoyama
  • Patent number: D881918
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: April 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Mizutani, Yasuhisa Kurata, Tatsushi Sawada, Hidematsu Hayashi, Taketoshi Saito, Tomoharu Aoyama
  • Patent number: D884725
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Mizutani, Yasuhisa Kurata, Tatsushi Sawada, Hidematsu Hayashi, Taketoshi Saito, Tomoharu Aoyama
  • Patent number: D894923
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 1, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Mizutani, Yasuhisa Kurata, Tatsushi Sawada, Hidematsu Hayashi, Taketoshi Saito, Tomoharu Aoyama