Abstract: A multichip module comprising: a base substrate; a wiring board disposed on the base substrate and having a wiring pattern; an adhesive layer configured to bond the base substrate to the wiring board while maintaining an electrical connection between the base substrate and the wiring board; and a plurality of chips connected to a surface of the wiring board, the surface being opposite the adhesive layer, wherein, assuming that ? is a coefficient of thermal expansion of the wiring board, ? is a coefficient of thermal expansion of the base substrate, and ? is a coefficient of thermal expansion of the adhesive layer, the relationship ?<?<? is satisfied.

Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.

Abstract: An electric circuit apparatus includes: a first-circuit board that includes a first-through-hole, and a first-electrode disposed on a front side of the first-circuit-board; a second-circuit-board that is disposed on a back side of the first-circuit-board, the second-circuit-board including on the front side of the second-circuit-board a second-electrode associated with the first-through-hole; a semiconductor device that is disposed on the front side of the first-circuit-board, the semiconductor device including on a back side a third-electrode-associated with the first-electrode, and a fourth-electrode-associated with the second-electrode; a first-bonding-material that bonds the first-electrode and the-third-electrode; a second-bonding-material that bonds the second-electrode and the fourth-electrode while passing through the first-through-hole; and a support body that is disposed between the first-electrode and the second-circuit-board and that supports the first-circuit-board.

Abstract: A wiring substrate includes: a substrate; an insulator formed in the substrate and having a through hole; an electrode formed in the substrate and provided within the through hole; and a conductor bonded to the electrode and provided within the through hole, wherein the through hole has a shape that is widened toward a direction away from the substrate, and the conductor is configured to cover the entire top surface of the electrode and has a shape that is widened toward the direction away from the substrate.

Abstract: A method of manufacturing a multi-chip module includes: securing a plurality of chips on a surface of a flat-shaped member through a solder bump; connecting the plurality of chips with each other by a bonding wire, at surfaces, opposite to the flat-shaped member side, of the plurality of chips; and electrically connecting the plurality of chips with a board, at the surfaces, opposite to the flat-shaped member side, of the plurality of chips.

Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Abstract: A first generating part assumes that a circuit board is a laminated body of a lower layer portion and an upper layer portion and sets a thermal expansion coefficient of the circuit board itself having been actually measured in advance as a thermal expansion coefficient ?1 of the lower layer portion. Further, the first generating portion sets a value obtained by a Stoney's equation as a thermal expansion coefficient ?2 of the upper layer portion. Then, the laminated body of the lower layer portion and the upper layer portion is segmented into a plurality of grid data and element segment data in which a position and a material of grid data are made to correspond to each other is generated. The second calculating part calculates a physical amount occurring in an analysis object based on a finite element with a variety of solvers, and outputs an analysis result. In other words, the second calculating part performs a simulation of behavior of the analysis object.

Abstract: A first generation portion divides an object to be analyzed into a plurality of finite elements to generate element division data. A first calculation portion defines and calculates a plurality of meshes dividing the object to be analyzed into units larger than the finite elements. A second generation portion assumes that a friction layer which has a thickness of “0” and a friction coefficient between a conductive material and a composite material of a predetermined value less than 1 exists at the interface between the conductive material and the composite material, and the second generation portion generates mesh data. A second calculation portion uses various solvers to calculate the physical amounts produced in the object to be analyzed on the basis of the mesh data and outputs the analysis result. In other words, the second calculation portion performs a simulation of the behavior of the object to be analyzed.

Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Abstract: A semiconductor device includes a first circuit base member including a surface having multiple first electrodes formed thereon, a second circuit base member being provided above the first circuit base member and having first through holes and second through holes formed respectively above the first electrodes, a semiconductor package provided above the second circuit base member, and multiple first bumps provided inside the first through holes and the second through holes to connect the first electrodes to the semiconductor package.

Abstract: An interconnect board for interconnecting and arranged between a first circuit board and a second circuit board, the interconnect board includes a conductive plate including a connection terminal to be electrically connected to a power supply terminal or a ground terminal of each of the first circuit board and the second circuit board, an insulating member wrapping the conductive plate except for the connection terminal, and a conductive member penetrating the insulating member to electrically connect a signal terminal of the first circuit board to a signal terminal of the second circuit board.

Abstract: A method of manufacturing a multi-chip module includes: securing a plurality of chips on a surface of a flat-shaped member through a solder bump; connecting the plurality of chips with each other by a bonding wire, at surfaces, opposite to the flat-shaped member side, of the plurality of chips; and electrically connecting the plurality of chips with a board, at the surfaces, opposite to the flat-shaped member side, of the plurality of chips.

Abstract: A multichip module comprising: a base substrate; a wiring board disposed on the base substrate and having a wiring pattern; an adhesive layer configured to bond the base substrate to the wiring board while maintaining an electrical connection between the base substrate and the wiring board; and a plurality of chips connected to a surface of the wiring board, the surface being opposite the adhesive layer, wherein, assuming that ? is a coefficient of thermal expansion of the wiring board, ? is a coefficient of thermal expansion of the base substrate, and ? is a coefficient of thermal expansion of the adhesive layer, the relationship ?<?<? is satisfied.

Abstract: A circuit board for reducing a transmission loss and a method for manufacturing the circuit board. In the circuit board including a ground layer and power layer facing each other, a wiring layer disposed between the ground layer and the power layer, and an insulating section formed between the ground layer and the power layer so as to sandwich the wiring layer therebetween, a low dielectric loss layer having a dielectric tangent lower than that of the insulating section is formed at least on an upper or lower surface of the wiring layer. According to such a circuit board, the low dielectric loss layer is formed on an interface between the insulating section and the wiring layer, and therefore, a transmission loss in a high frequency region is reduced.

Abstract: A semiconductor device has a semiconductor element having a plurality of connection terminals, a circuit substrate electrically connected with the semiconductor element; and a connecting member arranged between the semiconductor element and the circuit substrate having a plurality of conductive projections each having a columnar portion, each of columnar portions are connected with each of connection terminals, a cross section of the columnar portion along a plane parallel to a surface of the semiconductor element being smaller than a surface area of each of connection terminals of the semiconductor element.

Abstract: An inexpensive multilayer wiring circuit board capable of conducting high frequency switching operation on the circuit while the generation of high frequency noise is being suppressed by reducing the inductance of the circuit in provided. A multilayer wiring circuit board with an uppermost layer designated as a first layer on which parts are mounted; a second layer on which one of a ground layer and an electric power source layer is arranged; a third layer on which the other is arranged; and an insulating layer arranged between the ground layer and the electric power source layer. A resin layer having a thermoplastic adhesion property on both faces is used as material of the insulating layer arranged between the electric power source layer and the ground layer.

Abstract: A first generation portion divides an object to be analyzed into a plurality of finite elements to generate element division data. A first calculation portion defines and calculates a plurality of meshes dividing the object to be analyzed into units larger than the finite elements. A second generation portion assumes that a friction layer which has a thickness of “0” and a friction coefficient between a conductive material and a composite material of a predetermined value less than 1 exists at the interface between the conductive material and the composite material, and the second generation portion generates mesh data. A second calculation portion uses various solvers to calculate the physical amounts produced in the object to be analyzed on the basis of the mesh data and outputs the analysis result. In other words, the second calculation portion performs a simulation of the behavior of the object to be analyzed. The simulation is performed within an arbitrary temperature range set by a user.

Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.

Abstract: A semiconductor device has a semiconductor element having a plurality of connection terminals, a circuit substrate electrically connected with the semiconductor element; and a connecting member arranged between the semiconductor element and the circuit substrate having a plurality of conductive projections each having a columnar portion, each of columnar portions are connected with each of connection terminals, a cross section of the columnar portion along a plane parallel to a surface of the semiconductor element being smaller than a surface area of each of connection terminals of the semiconductor element.

Abstract: A circuit board for reducing a transmission loss and a method for manufacturing the circuit board. In the circuit board including a ground layer and power layer facing each other, a wiring layer disposed between the ground layer and the power layer, and an insulating section formed between the ground layer and the power layer so as to sandwich the wiring layer therebetween, a low dielectric loss layer having a dielectric tangent lower than that of the insulating section is formed at least on an upper or lower surface of the wiring layer. According to such a circuit board, the low dielectric loss layer is formed on an interface between the insulating section and the wiring layer, and therefore, a transmission loss in a high frequency region is reduced.