Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer on a substrate, forming a carbon nanotube (CNT) layer on the first dielectric layer, forming a second dielectric layer on the carbon nanotube (CNT) layer, patterning a plurality of trenches in the second dielectric layer exposing corresponding portions of the carbon nanotube (CNT) layer, forming a plurality of contacts respectively in the plurality of trenches on the exposed portions of the carbon nanotube (CNT) layer, performing a thermal annealing process to create end-bonds between the plurality of the contacts and the carbon nanotube (CNT) layer, and depositing a passivation layer on the plurality of the contacts and the second dielectric layer.

Abstract: Detectors and methods of forming the same include aligning a semiconducting carbon nanotubes on a substrate in parallel to form a nanotube layer. The aligned semiconducting carbon nanotubes in the nanotube layer are cut to a uniform length corresponding to a detection frequency. Metal contacts are formed at opposite ends of the nanotube layer.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.

Abstract: Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

Abstract: Aspects of the present disclosure relate to a security device, in particular, a multilayered security device. The multilayered security device includes a substrate layer having a first substrate. The substrate layer attaches to the product. The multilayered security device also includes a graphene layer. The graphene layer has a first continuous graphene sheet that is made of a monolayer of covalently-bonded carbon atoms. The graphene layer also forms, in response to exposure to a verification stimulus, a contrasting pattern with respect to an exposed substrate area from the substrate layer.

Abstract: Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

Abstract: Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

Abstract: Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

Abstract: Aspects of the present disclosure relate to a security device, in particular, a multilayered security device. The multilayered security device includes a substrate layer having a first substrate. The substrate layer attaches to the product. The multilayered security device also includes a graphene layer. The graphene layer has a first continuous graphene sheet that is made of a monolayer of covalently-bonded carbon atoms. The graphene layer also forms, in response to exposure to a verification stimulus, a contrasting pattern with respect to an exposed substrate area from the substrate layer.

Abstract: Aspects of the present disclosure relate to a security device, in particular, a multilayered security device. The multilayered security device includes a substrate layer having a first substrate. The substrate layer attaches to the product. The multilayered security device also includes a graphene layer. The graphene layer has a first continuous graphene sheet that is made of a monolayer of covalently-bonded carbon atoms. The graphene layer also forms, in response to exposure to a verification stimulus, a contrasting pattern with respect to an exposed substrate area from the substrate layer.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.

Abstract: Embodiments are directed to a plasmonic structure having an enhanced resonance frequency bandwidth. In one aspect, a plasmon-enhanced coupler is provided having a first plasmon region and a second plasmon region. A resonance frequency bandwidth of the plasmon-enhanced coupler is a hybridization of at least one first resonance frequency of the first plasmon region, and at least one second resonance frequency of the second plasmon region. The first plasmon region may be implemented as a single layer of graphene conductive material, and the second plasmon region may be implemented as multiple layers of graphene conductive material. The resonance frequency bandwidth may be chosen to overlap a frequency that comprises a vibration frequency of certain molecules of interest. Radiation directed to the plasmon-enhanced coupler causes its plasmons to interact with the molecules of interest, thereby altering the radiation.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.

Abstract: Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

Abstract: There are provided methods for functionalizing a planar surface of a microelectronic structure, by exposing the surface to at least one vapor including at least one functionalization species, such as NO2 or CH3ONO, that non-covalently bonds to the surface while providing a functionalization layer of chemically functional groups, to produce a functionalized surface. The functionalized surface is exposed to at least one vapor stabilization species that reacts with the functionalization layer to form a stabilization layer that stabilizes the functionalization layer against desorption from the planar microelectronic surface while providing chemically functional groups. The stabilized surface is exposed to at least one material layer precursor species that deposits a material layer on the stabilized planar microelectronic surface. The stabilized planar microelectronic surface can be annealed at a peak annealing temperature that is less than about 700° C.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: Aspects of the present disclosure relate to a security device, in particular, a multilayered security device. The multilayered security device includes a substrate layer having a first substrate. The substrate layer attaches to the product. The multilayered security device also includes a graphene layer. The graphene layer has a first continuous graphene sheet that is made of a monolayer of covalently-bonded carbon atoms. The graphene layer also forms, in response to exposure to a verification stimulus, a contrasting pattern with respect to an exposed substrate area from the substrate layer.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.