Abstract: A thin film transistor includes a gate, an insulating medium layer and a Schottky diode. The Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode is located on the surface of the insulating medium layer and includes a first metal layer and a second metal layer. The second electrode is located on the surface of the insulating medium layer and includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a nano-scale semiconductor structure.

Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate on the substrate; a dielectric layer on the gate, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer formed by magnetron sputtering and in direct contact with the gate; a semiconductor layer on the dielectric layer, wherein the semiconductor layer includes nano-scaled semiconductor materials; and a source and a drain, wherein the source and the drain are on the dielectric layer, spaced apart from each other, and electrically connected to the semiconductor layer. The thin film transistor almost has no current hysteresis.

Abstract: The disclosure relates to a logic circuit. The logic circuit includes a n-type thin film transistor and a p-type thin film transistor. Each thin film transistor includes a substrate; a semiconductor layer including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The n-type thin film transistor and the p-type thin film transistor share the same substrate and the same gate.

Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the first sub-dielectric layer. The thin film transistor almost has no current hysteresis.

Abstract: The disclosure relates to a logic circuit. The logic circuit includes two ambipolar thin film transistors. Each of the two ambipolar thin film transistors includes a substrate; a semiconductor layer located on the substrate and including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are located on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer located on the substrate and covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The two ambipolar thin film transistors share the same substrate, the same gate, and the same drain.

Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate located on the substrate; a dielectric layer located on the gate; a semiconductor layer located on the dielectric layer and including nano-scaled semiconductor materials; and a drain and a source spaced apart from each other and electrically connected to the semiconductor layer. The dielectric layer is an oxide layer formed by magnetron sputtering and in direct contact with the gate. The thin film transistor has inverse current hysteresis.

Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer is an oxide dielectric layer formed by magnetron sputtering; and a gate in direct contact with the dielectric layer. The thin film transistor has inverse current hysteresis.

Abstract: A metal oxide semiconductor carbon nanotube thin film transistor circuit includes a p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Abstract: The invention proposes an apparatus for reducing motion artifact in an ECG signal of a patient. The apparatus comprises a calculating unit configured to calculate a mean value beat from the ECG signal; a first obtaining unit configured to obtain a residual signal based on the ECG signal and the mean value beat calculated from the ECG signal; a filtering unit configured to perform filtering of the residual signal with one or more cut off frequencies; a second obtaining unit configured to obtain a modified ECG signal based on the filtered residual signal and the mean value beat; and a determining unit configured to determine the one or more cut off frequencies of the filtering based on an acceleration signal representative of motion status of the patient. By using the proposed apparatus, motion artifacts can be greatly removed from the ECG signal and the quality of the ECG signal can be therefore improved.

Abstract: A brush for an electric motor has a brush body having a front end surface configured to make sliding electrical contact with a commutator of the motor. First and second side surfaces are connected to the front end surface. The first side surface and the second side surface are positioned on opposite sides of the brush body in a rotational direction of the commutator. The front end surface has a first contact surface and a second contact surface that contact the commutator earlier than other regions of the front end surface, and are respectively positioned on diametrically opposed corners of the front end surface. In an initial state, the width of the contact area between the brush and the commutator is increased to extend the commutation time.

Abstract: The present invention provides a method and apparatus for reducing motion artifacts in ECG signals. According to an aspect of the present invention, there is proposed a method of reducing motion artifacts in ECG signals, comprising: acquiring a current beat from a continuously measured ECG signal of a patient; calculating a correlation coefficient between a previous mean value beat and the current beat in the ECG signal; determining the weights to be assigned to the previous mean value beat and the current beat based on the correlation coefficient; and calculating a current mean value beat based on the previous mean value beat, the current beat, and the weights thereof. Accordingly, the novel method of deriving the current mean value beat may reduce ECG artifacts due to patient movement in such a manner that the SNR of the ECG signal can be improved substantially.

Abstract: A metal oxide semiconductor carbon nanotube thin film transistor circuit includes a p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Abstract: A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Abstract: The present invention provides a method for spine position detection, comprising: obtaining 2D geometrical configuration of a current vertebra body selected from a plurality of vertebra bodies visible in an image on a sagittal plane defined by a horizontal component of an initial point, a geometrical template being applied to the current vertebra body and the 2D geometrical configuration of the current vertebra body being adjusted by a predetermined correlation evaluation; searching adjacent edge points of next vertebra body corresponding to a number of edge points of the current vertebra body by identifying the gradient values along the direction substantially perpendicular to the edge of the current vertebra body based on the adjusted 2D geometrical configuration of the current vertebra body; calculating height of an intervertebral disc located between the current vertebra body and the next vertebra body based on an average of the distances between the edge points of the current vertebra body and the corres

Abstract: There provides an apparatus for recognizing a head region in a CT lateral image of a subject, comprising: a deriving unit for deriving a first image representing a bone of the subject from the CT lateral image; an extracting unit for extracting a boundary curve indicating an outer contour of a region comprising at least part of the occipital bone and at least part of the cervical vertebra of the subject in the first image; and a determining unit for determining a first pixel position indicating a bottommost point of the head region of the subject, based on a shape feature parameter of the boundary curve.