Patents by Inventor Daniel Bryce Thompson

Daniel Bryce Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11728460
    Abstract: Disclosed herein are techniques for reducing the pitch between light-emitting diodes (LEDs) in an array of LEDs. According to an aspect of the invention, a method includes forming a plurality of stacks of layers on a surface of a semiconductor, with a p contact at an interface between each stack and a p-type layer of the semiconductor. The semiconductor is etched to form a plurality of mesa shapes corresponding to the plurality of stacks. A dielectric is formed on at least a portion of each mesa shape and at least a portion of each stack. A reflector is formed on at least a portion of the dielectric and at least a portion of the semiconductor to provide an n contact at an interface between the reflector and an n-type layer of the semiconductor. The reflector is physically separated from the p contact for each stack.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: August 15, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Daniel Bryce Thompson, James Small
  • Patent number: 11631784
    Abstract: Disclosed herein is an apparatus including a first three-dimensional (3-D) structure, a second 3-D structure, and a conductive layer. The first 3D structure includes a first-type doped semiconductor material having a semi-polar facet. The second 3-D structure forms a light-emitting diode (LED) and includes a second-type doped semiconductor material, an active layer, and the first-type doped semiconductor material. The conductive layer at least partially overlays and is in ohmic contact with the semi-polar facet. The conductive layer is configured to carry current that flows between the semi-polar facet and the active layer. In some embodiments, the first-type doped semiconductor material may include an N-type doped semiconductor material, and the second-type doped semiconductor material may include a P-type doped semiconductor material. The first-type doped semiconductor material of both 3-D structures may be etched from a common first-type doped semiconductor epitaxial layer.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: April 18, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventor: Daniel Bryce Thompson
  • Patent number: 11611026
    Abstract: Described are light emitting apparatus with self-aligned elements and techniques for manufacturing such light emitting apparatus. In certain embodiments, a method for manufacturing a light emitting apparatus involves forming a plurality of semiconductor layers including a first semiconductor layer, a second semiconductor layer, and a light emission layer between the first semiconductor layer and the second semiconductor layer. The method further involves forming an electrical contact and a spacer. The electrical contact is formed on a surface of the first semiconductor layer. The spacer is formed on the surface of the first semiconductor layer, around the electrical contact. After forming the spacer, the plurality of semiconductor layers is etched to form a mesa with sidewalls that extend from an outer edge of the spacer. The spacer operates as an etch mask that causes the electrical contact to be substantially centered between opposing sidewalls of the mesa.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: March 21, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Daniel Bryce Thompson, James Small
  • Publication number: 20220271207
    Abstract: Techniques disclosed herein relate to micro light emitting diodes (micro-LEDs) for a display system. A display system includes an array of micro light emitting diodes (micro-LEDs), an array of output couplers optically coupled to the array of micro-LEDs and configured to extract light emitted by respective micro-LEDs in the array of micro-LEDs, a waveguide display, and display optics configured to couple the light emitted by the array of micro-LEDs and extracted by the array of output couplers into the waveguide display. Each output coupler in the array of output couplers is configured to direct a chief ray of the light emitted by a respective micro-LED in the array of micro-LEDs to a different respective direction.
    Type: Application
    Filed: March 9, 2022
    Publication date: August 25, 2022
    Inventors: Stephan Lutgen, François Gérard Franck Olivier, Vasily Zabelin, William Padraic Henry, Markus Broell, Thomas Lauermann, David Massoubre, Daniel Bryce Thompson, Michael Grundmann
  • Publication number: 20220131041
    Abstract: Disclosed herein are techniques for reducing the pitch between light-emitting diodes (LEDs) in an array of LEDs. According to an aspect of the invention, a method includes forming a plurality of stacks of layers on a surface of a semiconductor, with a p contact at an interface between each stack and a p-type layer of the semiconductor. The semiconductor is etched to form a plurality of mesa shapes corresponding to the plurality of stacks. A dielectric is formed on at least a portion of each mesa shape and at least a portion of each stack. A reflector is formed on at least a portion of the dielectric and at least a portion of the semiconductor to provide an n contact at an interface between the reflector and an n-type layer of the semiconductor. The reflector is physically separated from the p contact for each stack.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 28, 2022
    Inventors: Daniel Bryce THOMPSON, James SMALL
  • Patent number: 11309464
    Abstract: Techniques disclosed herein relate to micro light emitting diodes (micro-LEDs) for a display system. A display system includes an array of micro light emitting diodes (micro-LEDs), an array of output couplers optically coupled to the array of micro-LEDs and configured to extract light emitted by respective micro-LEDs in the array of micro-LEDs, a waveguide display, and display optics configured to couple the light emitted by the array of micro-LEDs and extracted by the array of output couplers into the waveguide display. Each output coupler in the array of output couplers is configured to direct a chief ray of the light emitted by a respective micro-LED in the array of micro-LEDs to a different respective direction.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: April 19, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Stephan Lutgen, François Gérard Franck Olivier, Vasily Zabelin, William Padraic Henry, Markus Broell, Thomas Lauermann, David Massoubre, Daniel Bryce Thompson, Michael Grundmann
  • Patent number: 11245055
    Abstract: Disclosed herein are techniques for reducing the pitch between light-emitting diodes (LEDs) in an array of LEDs. According to an aspect of the invention, a device includes an array having a plurality of LEDs and a reflector that is in Ohmic contact with at least two adjacent LEDs of the plurality of LEDs. Each LED of the plurality of LEDs includes a p contact, and the reflector is physically separated from the p contact of each LED of the plurality of LEDs.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: February 8, 2022
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Daniel Bryce Thompson, James Small
  • Publication number: 20220037557
    Abstract: Disclosed herein is an apparatus including a first three-dimensional (3-D) structure, a second 3-D structure, and a conductive layer. The first 3D structure includes a first-type doped semiconductor material having a semi-polar facet. The second 3-D structure forms a light-emitting diode (LED) and includes a second-type doped semiconductor material, an active layer, and the first-type doped semiconductor material. The conductive layer at least partially overlays and is in ohmic contact with the semi-polar facet. The conductive layer is configured to carry current that flows between the semi-polar facet and the active layer. In some embodiments, the first-type doped semiconductor material may include an N-type doped semiconductor material, and the second-type doped semiconductor material may include a P-type doped semiconductor material. The first-type doped semiconductor material of both 3-D structures may be etched from a common first-type doped semiconductor epitaxial layer.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 3, 2022
    Inventor: Daniel Bryce THOMPSON
  • Patent number: 11164995
    Abstract: Disclosed herein is an apparatus including a first three-dimensional (3-D) structure and a second 3-D structure. The first 3-D structure may include a first-type doped semiconductor material having semi-polar facets. The second 3-D structure may form a light-emitting diode (LED). The second 3-D structure may include a second-type doped semiconductor material, an active layer, and the first-type doped semiconductor material. The apparatus may also include a conductive layer which at least partially overlays and is in ohmic contact with the semi-polar facets of the first-type doped semiconductor material. The first-type doped semiconductor material of the first 3-D structure and the first-type doped semiconductor material of the second 3-D structure may be etched from a common first-type doped semiconductor epitaxial layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: November 2, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventor: Daniel Bryce Thompson
  • Patent number: 11152533
    Abstract: Techniques are disclosed for utilizing an etchant-accessible carrier substrate that enables etching through the carrier substrate. More particularly, an etchant is provided access to the adhesive layer via the etchant-accessible carrier substrate via one or more holes in the etchant-accessible carrier substrate. The size and/or pattern of the holes may vary, depending on desired functionality. The etching process may be optionally stopped prior to the removal of all of the adhesive layer such that at least a portion of the adhesive layer remains, which can help ensure the light-emitting structures do not slip off of the etchant-accessible carrier substrate as the etchant-accessible carrier substrate is moved from one location to another during the fabrication process.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 19, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Daniel Bryce Thompson, Daniel Brodoceanu, Pooya Saketi
  • Publication number: 20210265526
    Abstract: Disclosed herein is an apparatus including a first three-dimensional (3-D) structure and a second 3-D structure. The first 3-D structure may include a first-type doped semiconductor material having semi-polar facets. The second 3-D structure may form a light-emitting diode (LED). The second 3-D structure may include a second-type doped semiconductor material, an active layer, and the first-type doped semiconductor material. The apparatus may also include a conductive layer which at least partially overlays and is in ohmic contact with the semi-polar facets of the first-type doped semiconductor material. The first-type doped semiconductor material of the first 3-D structure and the first-type doped semiconductor material of the second 3-D structure may be etched from a common first-type doped semiconductor epitaxial layer.
    Type: Application
    Filed: March 5, 2020
    Publication date: August 26, 2021
    Inventor: Daniel Bryce THOMPSON
  • Patent number: 11101418
    Abstract: Described are light emitting apparatus with self-aligned elements and techniques for manufacturing such light emitting apparatus. In certain embodiments, a light emitting apparatus includes a mesa formed by a plurality of semiconductor layers. The light emitting apparatus further includes an electrical contact on one of the semiconductor layers and a spacer around the electrical contact. The spacer is aligned with respect to the electrical contact, which permits etching around the spacer to define the shape of the mesa in such a way that the mesa is also aligned with respect to the electrical contact. In particular, the electrical contact is substantially centered between opposing sidewalls of the mesa.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 24, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Daniel Bryce Thompson, James Small
  • Publication number: 20210111319
    Abstract: Techniques disclosed herein relate to micro light emitting diodes (micro-LEDs) for a display system. A display system includes an array of micro light emitting diodes (micro-LEDs), an array of output couplers optically coupled to the array of micro-LEDs and configured to extract light emitted by respective micro-LEDs in the array of micro-LEDs, a waveguide display, and display optics configured to couple the light emitted by the array of micro-LEDs and extracted by the array of output couplers into the waveguide display. Each output coupler in the array of output couplers is configured to direct a chief ray of the light emitted by a respective micro-LED in the array of micro-LEDs to a different respective direction.
    Type: Application
    Filed: April 3, 2020
    Publication date: April 15, 2021
    Inventors: Stephan Lutgen, François Gérard Franck Olivier, Vasily Zabelin, William Padraic Henry, Markus Broell, Thomas Lauermann, David Massoubre, Daniel Bryce Thompson, Michael Grundmann
  • Publication number: 20200381588
    Abstract: Disclosed herein are techniques for reducing the pitch between light-emitting diodes (LEDs) in an array of LEDs. According to an aspect of the invention, a device includes an array having a plurality of LEDs and a reflector that is in Ohmic contact with at least two adjacent LEDs of the plurality of LEDs. Each LED of the plurality of LEDs includes a p contact, and the reflector is physically separated from the p contact of each LED of the plurality of LEDs.
    Type: Application
    Filed: October 23, 2019
    Publication date: December 3, 2020
    Inventors: Daniel Bryce THOMPSON, James SMALL
  • Patent number: 10770634
    Abstract: Disclosed are techniques related to reflectors having overall mesa shapes. Such a reflector may be formed over an overall mesa-shaped, layered structure of an apparatus for emitting light. The overall mesa-shaped, layered structure may comprise a mesa complement structure, a first-type doped semiconductor, a light emission layer, and a second-type doped semiconductor arranged in layers. Thus, the reflector may be configured to collimate light that emits from the light emission layer and reaches the reflector through the mesa complement structure.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 8, 2020
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Daniel Bryce Thompson, James Small
  • Patent number: 10763389
    Abstract: Described herein are light emitting apparatuses with minimized light emission areas and methods for fabricating such apparatuses. In certain embodiments, the emission area corresponds to an area of an electrical contact and is minimized by minimizing the area of the electrical contact. The electrical contact is configured to receive an electrical signal that causes a light emission layer to generate light. The light emission layer is between a first semiconductor layer and a second semiconductor layer, with the electrical contact being formed on the second semiconductor layer. To protect the second semiconductor layer from damage during an etching process, a conductive body is formed around the electrical contact, where the conductive body is a non-ohmic contact to the second semiconductor layer. The conductive body acts as an etch stop against unintended etching of the second semiconductor layer as a result of an alignment error during the etching process.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 1, 2020
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventor: Daniel Bryce Thompson
  • Patent number: 10483319
    Abstract: A pixelated display device and a method for making the same are disclosed. The device may include an array of nanowire LEDs located above a substrate. When the nanowire LEDs are initially grown, they may emit first-wavelength light proximally to the substrate and second-wavelength light distally from the substrate. The nanowires may remain as initially grown, in which case only second-wavelength light is visible, or the second-wavelength light emitting portions may be etched away such that only first-wavelength light is visible.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 19, 2019
    Assignee: GLO AB
    Inventors: Nathan Gardner, Ronald Kaneshiro, Daniel Bryce Thompson, Fariba Danesh, Martin Schubert
  • Patent number: 10229899
    Abstract: A laser liftoff process is provided. A device layer can be provided on a transfer substrate. Channels can be formed through the device layer such that devices comprising remaining portions of the device layer are laterally isolated from one another by the channels. The transfer substrate can be bonded to a target substrate through an adhesion layer. Surface portions of the devices can be removed from an interface region between the transfer substrate and the devices by irradiating a laser beam through the transfer substrate onto the devices. The laser irradiation decomposes the III-V compound semiconductor material. The channels provide escape paths for the gaseous products (such as nitrogen gas) that are generated by the laser irradiation. The transfer substrate is separated from a bonded assembly including the target substrate and remaining portions of the devices. The devices can include a III-V compound semiconductor material.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: March 12, 2019
    Assignee: GLO AB
    Inventor: Daniel Bryce Thompson
  • Patent number: 10217911
    Abstract: A set of light emitting devices can be formed on a substrate A growth mask having a first aperture in a first area and a second aperture in a second area is formed on a substrate. A first nanowire and a second nanowire are formed in the first and second apertures, respectively. The first nanowire includes a first active region having a first band gap and a second active region having a second band gap. The first band gap is greater than the second hand gap. The second nanowire includes an active region having the first band gap and does not include, or is adjoined to, any material having the second band gap.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: February 26, 2019
    Assignee: GLO AB
    Inventors: Martin Schubert, Daniel Bryce Thompson, Michael Grundmann, Nathan Gardner
  • Patent number: 10177123
    Abstract: A backplane optionally having stepped horizontal surfaces and optionally embedding metal interconnect structures is provided. First conductive bonding structures are formed on first stepped horizontal surfaces. First light emitting devices on a first transfer substrate are disposed on the first conductive bonding structures, and a first subset of the first light emitting devices is bonded to the first conductive bonding structures. Laser irradiation can be employed to selectively disconnect the first subset of the first light emitting devices from the first transfer substrate while a second subset of the first light emitting devices remains attached to the first transfer substrate.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 8, 2019
    Assignee: GLO AB
    Inventors: Nathan Gardner, Fredrick A. Kish, Jr., Miljenko Modric, Anusha Pokhriyal, Daniel Bryce Thompson, Fariba Danesh, Sharon N. Farrens