Patents by Inventor Daniel Bryce Thompson

Daniel Bryce Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150179895
    Abstract: A submount for light emitting diode (LED) die includes a substrate containing a plurality of tubs configured to receive an LED die, and a plurality of integrated interconnects integrated into the substrate. At least a portion of the interconnects for each tub have an exposed portion on a side of the submount and at least some of the plurality of the interconnects are not connected to other interconnects in the submount.
    Type: Application
    Filed: November 21, 2014
    Publication date: June 25, 2015
    Inventors: Scott Brad Herner, Linda Romano, Daniel Bryce Thompson, Martin Schubert
  • Publication number: 20150171280
    Abstract: Various embodiments include methods of fabricating light emitting diode (LED) devices, such as nanowire LED devices, that include forming a layer of a transparent, electrically conductive material over at least a portion of a non-planar surface of an LED device, and depositing a layer of a dielectric material over at least a portion of the layer of transparent conductive material, wherein depositing the layer of dielectric material comprises at least one of: (a) depositing the layer using a chemical vapor deposition (CVD) process, (b) depositing the layer at a temperature of 200° C. or more, and (c) depositing the layer using one or more chemically active precursors for the dielectric material.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 18, 2015
    Inventors: Scott Brad HERNER, Daniel Bryce THOMPSON
  • Patent number: 9059355
    Abstract: A method of etching including providing a plurality of nanostructures extending away from a support, the support comprising a dielectric layer located between the plurality of nanowires, forming a patterned mask over a first portion of the plurality of nanostructures, such that a second portion of the plurality of nanostructures are exposed and are not located under the patterned mask, etching the second portion of the plurality of nanostructures to remove at least a portion of the patterned mask and the second portion of the plurality of nanostructures, monitoring at least one gaseous byproduct of the etching of the plurality of nanostructures during the etching of the plurality of nanostructures and stopping the etching on detecting that the dielectric layer is substantially removed.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: June 16, 2015
    Assignee: GLO AB
    Inventor: Daniel Bryce Thompson
  • Publication number: 20150144968
    Abstract: A method of dicing semiconductor devices includes depositing a continuous first layer over the substrate, such that the first layer imparts a compressive stress to the substrate, and etching grooves in the first layer to increase local stress at the grooves compared to stress at the remainder of the first layer located over the substrate. The method also includes generating a pattern of defects in the substrate with a laser beam, such that a location of the defects in the pattern of defects substantially corresponds to a location of at least some of the grooves in the in the first layer, and applying pressure to the substrate to dice the substrate along the grooves.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Scott Brad Herner, Linda Romano, Daniel Bryce Thompson, Martin Schubert
  • Publication number: 20140370625
    Abstract: A method of etching including providing a plurality of nanostructures extending away from a support, the support comprising a dielectric layer located between the plurality of nanowires, forming a patterned mask over a first portion of the plurality of nanostructures, such that a second portion of the plurality of nanostructures are exposed and are not located under the patterned mask, etching the second portion of the plurality of nanostructures to remove at least a portion of the patterned mask and the second portion of the plurality of nanostructures, monitoring at least one gaseous byproduct of the etching of the plurality of nanostructures during the etching of the plurality of nanostructures and stopping the etching on detecting that the dielectric layer is substantially removed.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 18, 2014
    Inventor: Daniel Bryce Thompson
  • Publication number: 20140370631
    Abstract: Various embodiments include methods of fabricating a semiconductor device that include providing a plurality of nanostructures extending away from a support, forming a flowable material layer between the nanostructures, forming a patterned mask over a first portion of the flowable material and the first portion of the plurality of nanostructures, such that a second portion of the flowable material and a second portion of the plurality of nanostructures are not located under the patterned mask and etching the second portion of the flowable material and the second portion of the plurality of nanostructures to remove the second portion of the flowable material and the second portion of the plurality of nanostructures to leave the first portion of the flowable material and the first portion of the plurality of nanostructures unetched.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 18, 2014
    Inventors: Daniel Bryce Thompson, Cynthia Lemay
  • Publication number: 20140117307
    Abstract: A method for treating a LED structure with a substance, the LED structure includes an array of nanowires on a planar support. The method includes producing the substance at a source and causing it to move to the array along a line. The angle between the line followed by the substance and the plane of the support is less than 90° when measured from the center of the support. The substance is capable of rendering a portion of the nanowires nonconductive or less conductive compared to before being treated by the substance.
    Type: Application
    Filed: October 22, 2013
    Publication date: May 1, 2014
    Applicant: Glo AB
    Inventors: Scott Brad Herner, Daniel Bryce Thompson, Cynthia Lemay