Abstract: Circuit board insertion circuitry is used in conjunction with a staggered electrical connector. The insertion circuitry includes an isolated circuit which receives a high system voltage upon first stage contact between the card and a high voltage bus, and uses that high system voltage to tristate the output of a transceiver on the circuit board prior to second stage contact being made between the transceiver and the backplane data bus. Override circuitry for overriding the tristating effects of the isolating circuit are provided such that when the bias circuit which controls the transceiver output is properly powered, the bias circuit will control the transceiver output, and not the isolated circuit. Additional circuitry which isolates the circuit board so that a power fault on the board will not impact other boards on the backplane is also provided.

Abstract: A two stage desynchronizer is provided to receive a gapped data component of an STS-3C (STM-1) signal and provide therefrom an ungapped DS-4NA (E4) data signal. The first stage includes a data byte formation block which takes the gapped STS-3C payload data and formulates the data into bytes, a first FIFO which receives the bytes, and a first FIFO read controller which utilizes the STS-3C clock signal and causes bytes of data to be read out according to a schedule which reads bytes eight or nine times out of every ten STS-3C clock cycles. For each row (270 byte times) of the STS-3C frame, either 241 or 242 bytes are read out of the FIFO according to a slightly gapped schedule where the reading of the 242nd byte at least partially depends upon the number of stuffs in the signal and the pointer movements received. The second stage of the desynchronizer includes a second FIFO, a FIFO fullness measurement block, and a VCXO.

Abstract: A digital clock dejitter circuit has a RAM for receiving an incoming gapped signal, a digital, fractional RAM fullness gauge for tracking the average input and output rates to and from the RAM and for generating therefrom a control indication, and a controllable digital frequency generator for receiving a fast clock signal and the control indication, and for providing therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal. The RAM fullness gauge has write and read counters which track the movement of data into and out of the RAM, and a subtractor for taking the difference of the counters to obtain the integer value of the RAM depth. The controllable digital frequency generator has an adder, a register, and a fast clock counter (FCC) which provides the fullness gauge with a fractional digital indication of the RAM depth.

Abstract: Clock dejitter circuits are provided and comprise control circuits for generating a plurality of pulses over a clock cycle, and clock circuits for tracking the speeds of jittered incoming data signal and based on those speeds, and utilizing the plurality of pulses generating substantially unjittered data signals at the nominal rates of the jittered incoming signals. A control circuit broadly includes a divide by value x-divide by value x+1 circuit which receives a fast input clock signal, a modulus y counter, and a count decode for providing z control pulses over the count of y, and a logic gate for taking the outputs from the count decode and controlling the divide block to guarantee hat the divide block divides the fast input clock signal by value x q times for every r times the divide block divides the fast input clock signal by value x+1; wherein q plus r equals y, and z equals either q+1 or r+1.

Abstract: Apparatus and methods for modifying the address field of a packet are disclosed. The apparatus preferably includes an HDLC controller which finds the start of the packet and generates a signal indicative of the same, a sequence controller which receives the signal from the HDLC controller and controls the apparatus in response thereto, an address decoder receives the address field bytes from the HDLC controller and decodes them to provide a DLCI code therefrom, a RAM which is programmed as a DLCI translation table with outgoing DLCI codes being located at addresses which equate to the incoming DLCI codes, an address encoder which receives the outgoing DLCI code from the RAM and generates therefrom outgoing address field bytes, and a FIFO for storing the outgoing address field bytes until output is possible. Bytes received by the HDLC controller during the modification of the packet header are stored by the HDLC controller until the outgoing address field bytes are received at the FIFO.

Abstract: An apparatus which receives a gapped data component of an STS-1 signal and provides therefrom an ungapped DS-3 data signal is provided and includes a FIFO for receiving the data component of the STS-1 signal, a measuring circuit having an input clock related to the STS-1 signal and the output clock of the apparatus as inputs for effectively measuring the relative fullness of the FIFO, and a voltage controlled crystal oscillator (VCXO) for receiving a control signal from the measuring circuit and for generating the output clock of the apparatus in response thereto, where data in the FIFO is taken out of the FIFO as the DS-3 signal according to the rate of the output clock. The FIFO is preferably a byte wide RAM, and the measuring circuit is comprised of two counters, an XOR gate, and a low pass filter. One counter receives the apparatus output clock as its input, while the other counter receives a gapped STS-1 data payload input clock as its input.

Abstract: An apparatus and method for transferring a data payload (SPE) from a first substantially SONET signal into a second substantially SONET signal of different frequency is provided. The apparatus has: a circuit for extracting the SPE from the first SONET signal and sending the bytes of the SPE, according to a first clock, to a FIFO for storage; a circuit for obtaining the SPE bytes from the FIFO according to a second clock, for building the SPE into the second substantially SONET signal; and a circuit for comparing the relative byte phases of the first and second clocks. The byte phase comparison circuit serves two functions. In order to avoid read/write conflicts in the FIFO, it generates and sends a signal to the extracting circuit which causes the extracting circuit to change the byte phase (i.e. timing) at which bytes are sent to the FIFO.

Abstract: The transversal filter has a plurality of variable delay lines each having multiple voltage controlled delay stages in series, with one of the variable delay lines having a clock input, and the other variable delay lines having data signal inputs. A phase comparator is coupled to the output of two non-adjacent stages of the variable delay lines having the clock input. A feedback circuit is coupled to the comparator and provides voltage signals to the voltage controlled delay stages of all of the variable dealy lines, such that adjacent stages in a particular delay line are delayed in time equal fractions of a clock cycle from each other, and so that all delay lines are running on the same clock. A voltage weighting circuit is provided for shaping the voltage outputs of the data signal variable delay lines and the weighting circuit is coupled to the delay line stages by switches which are activated when a data signal is propagated through a delay line stage.

Abstract: A modular, expandable, non-blocking system for cross-connecting high speed digital signals is provided. The system is capable of connecting DSn, CEPTn, and STSn signals as desired, with lower rate signals being included as components of the high-rate signals or terminating on low speed lines, as desired. The system accomplishes its goals by converting all incoming signals into a substantially SONET format, and by processing all the signals in that format. The signals are typically cross-connected in the substantially SONET format, although an expandable non-blocking wide band cross-connect module is provided which cross-connects any like signals. If the outgoing signal is to be in other than SONET format, the substantially SONET formatted signal is reconverted into its outgoing format. To create a complete system, various modules are utilized, including: add/drop multiplexer means for add/drop applications of DS-0, DS-1, CEPTn signals, etc.

Abstract: A DS1 dejitter circuit has a control circuit for generating six pulses over a one hundred and ninety three 1.544 Mb/sec clock cycle, and a clock circuit for tracking the frequency of a jittered incoming DS1 signal, and based on that frequency, and utilizing the six pulses, generating a clean DS1 signal at the nominal rate of the jittered incoming signal. The control circuit preferably includes a divide by 28 or 29 circuit which receives a 44.736 Mb/sec (DS3) input clock signal, a mod 193 counter, and a count decoder for providing the six control pulses over the 193 count. Logic circuitry is provided for taking the outputs from the count decode and controlling the divide block to guarantee that the divide block divides the DS3 signal by 29 one hundred eighty-eight times for every five times the divide block divides the DS3 signal by 28. In this manner an average clock of 1.544 Mb/sec (the standard DS1) rate is obtained from the divide block.

Abstract: Switching components and switching networks utilizing a plurality of identical switching components are provided for cross-connecting virtual tributaries of a plurality of substantially SONET formatted signals. The switching components each receive at least one SONET formatted signal and disassemble the signal into its virtual tributary (VT) payload components while marking the V5 byte. The VT data is buffered and switched in phase, time, and space to effect the cross-connect onto SONET signal generating output buses which are synchronously clocked buses running through the components. The space switch is essentially a non-blocking switch matrix. The time switch is a comparison means associated with each incoming VT which compares the VT destination of the data in the buffer to a virtual tributary time indication based on the phase of the synchronous clocked output buses.

Abstract: A modular, expandable, non-blocking system for cross-connecting high speed digital signals is provided. The system is capable of connecting DSn, CEPTn, and STSn signals as desired, with lower rate signals being included as components of the high-rate signals or terminating on low speed lines, as desired. The system accomplishes its goals by converting all incoming signals into a substantially SONET format, and by processing all the signals in that format. The signals are typically cross-connected in the substantially SONET format, although an expandable non-blocking wide band cross-connect module is provided which cross-connects any like signals. If the outgoing signal is to be in other than SONET format, the substantially SONET formatted signal is reconverted into its outgoing format. To create a complete system, various modules are utilized, including: add/drop multiplexer means for add/drop applications of DS-0, DS-1, CEPTn signals, etc.

Abstract: A switching component preferably in integrated circuit form is provided. The switching component has a plurality of inlet and outlet data ports with associated inlet and outlet clock ports, a clock regenerator and a flip-flop for each outlet data port, and a switch matrix for coupling each inlet data port and its associated inlet clock port to any outlet data port and its associated outlet clock port. The clock regeneration means obtains the clock signal exiting the switching core and regenerates the clock signal waveshape. The flip-flop causes data exiting the switching core to be clocked out of the switching component synchronously with its associated regenerated clock signal according to the regenerated clock signal. A plurality of identical switching components can be arranged in a folded Clos arrangement having a plurality of stages to provide a desired switch network of any size.

Abstract: A telecommunication switching system includes a number of control circuits each of which is common to a plurality of line circuits and is coupled through time division multiplex links with two processor controlled interface circuits which are further coupled to a switching network. Line scanning information is processed in the control circuits to reduce the work load of the processor controlled interface circuits. Said line scanning information is then transmitted in the TDM links to the processor controlled interface circuits. The transmission priority among the control circuits is determined by a priority arrangement established for the system. A channel assignment controls the allocation of channels of the TDM links leading to parts of the line circuits.

Abstract: There is disclosed an apparatus for enabling one to increase the bandwidth of a multi-channel digital switching system. Essentially, the system allows one to set up multi-channel link paths to obtain a total band width of N times the bandwidth of a typical switching path in a digital switching network. To do this, a common frame counter is located in the unused bit positions of the sample in each of the paths, forming a wideband channel. At the receive end, the apparatus de-skews the received samples to properly reassembly the output. This operation is provided by utilizing one content addressable memory and an associated random access memory (CAM/RAM) (C/R) for each channel to be joined. The width of each C/R is twelve bits, eight for data, the read-out section and four for frame counter, which is the associative section. The length of each C/R is a function of the maximum skew to be counted.

Abstract: A duplex digital transmitter system is disclosed which permits simultaneous digital signal exchange over a two-wire loop. Two sets are provided at the ends of the loop, each having a three-port lattice adapted to separate the transmitted and received digital signals. The digital signals are encoded using a biphase scheme so that they have a zero D.C. component. Therefore the loop is used simultaneously to transmit D.C. power from one set to the other.

Abstract: A telephone line circuit and system for interfacing digital exchange line circuits to a terminal interface of a switching network is disclosed. The system includes controllable active circuit impedance matching means for reducing impedance mismatch between a selected line circuit and the terminal interface. Control means controls both the active circuit impedance matching means for adjusting the effective circuit impedance to a value within a predetermined range, and the conditioning circuit gain pads for selectably adjusting the gain of a transmitted signal. Additionally, control means controls the d.c. line impedance and voltage for adjusting the effective line feed current to the subscriber loop, and provides interfaces for a plurality of line circuits to both a switching network and external processor. Supervision means provides supervision control signals to the control means and thereby permits the telephone line circuit system to provide desired telephone system functions.

Abstract: A diagnostic system for a telecommunications system including a digital switching network is controlled via a plurality of data processors. Each of the distributed data processors has a unique address and has diagnostic data stored therein for use in performing diagnostics in the switching network. The switching network includes digital switching elements, each having bidirectional ports for receiving and transmitting digital signals, and each of the bidirectional ports also having a unique address in the network. Diagnostic paths are established under processor control between the digital switching elements and the data processors.

Abstract: A system is disclosed which permits information received from any data terminal or telephone subscriber line at any interface to a digital network to be transmitted to any number of other terminals at any or all of the interfaces to the digital network. The system herein described also permits any terminal at any interface of the digital network to be conferenced, with up to N other terminals at any or all of the interfaces to the digital network where N can be made to depend solely upon the topology and single path transmission delay of the digital network itself. A facility is provided which is independently provisioned at every interface to the digital network and which is independently and concurrently available to any number of combinations of terminals and simplex paths at those interfaces. A broadcast capability is also provided whereby telecommunication information can be simultaneously transmitted from a source terminal to a plurality of destination terminals.

Abstract: A multiport single sided switching element is described for providing space and time switching between the input ports thereof and the output ports thereof in response to digital command signals for frames of digitally encoded data in a plurality of channels which is phase (bit) asynchronously coupled to any port of the switching element, the command signals being in for example the same channels as is the data.