Abstract: Systems and methods are provided for converting input data streams having variable input sample rates to an output sample rate, which systems and methods are used in processing the data streams. In one embodiment, a system includes a clock source, a counter configured to count cycles for a corresponding data stream, and a data processor. The data processor is configured to read the number of cycles counted by the counter between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted.

Abstract: Systems and methods for converting a data stream from a first sample rate to a second sample rate using a sample rate converter that employs selectable filters. In one embodiment, the filters are implemented by providing multiple sets of filter coefficients in a memory, selecting one of the sets of filter coefficients and performing coefficient interpolation to produce filter coefficients that are convolved with the input data stream to produce a re-sampled output data stream. The input signal can be an audio signal that is convolved with interpolated polyphase filter coefficients in the sample rate converter of a digital PWM audio amplifier. The set of filter coefficients can be selected by a value stored in a filter selection register that is modifiable by a DSP or by user input. The sets of filter coefficients can be stored in a single memory and interpolated according to a cubic spline interpolation algorithm.

Abstract: A low delay corrector (LDC) unit includes a non-linear function generator and a filter. The nonlinear function generator receives a first signal and outputs a second signal in dependence on the first signal and a transfer function of the nonlinear function generator. The filter is fed in dependence on the second signal output by the nonlinear function generator. The first signal received by the nonlinear function generator is derived in dependence on an input signal provided to an input of the LDC unit and an output of the filter. An output of the LDC unit is derived in dependence on the first signal received by the nonlinear function generator and the second signal output by the nonlinear function generator.

Abstract: Systems and methods for converting a data stream from a first sample rate to a second sample rate, where the data is received in bursts. In one embodiment, a method includes receiving bursty audio data on a first input line and receiving synchronization data on a second input line that is separate from the first input line. An input sample rate is then estimated for the received audio data based on the received synchronization data and the audio data is converted to an output sample rate. The input sample rate is determined by counting samples received in a time interval and potentially low-pass filtering the result. The audio data may be in packetized, parallel, or other forms, and the synchronization data may include individual signals, such as pulses or bits received at regular or irregular intervals.

Abstract: Systems and methods for ensuring proper phase alignment of audio signals which are processed by separate hardware channels in an audio amplification system. In one embodiment, the phase alignment is controlled by determining the number of audio data samples which are stored in the input buffers of multiple audio amplification units and controlling reads from the input buffers to minimize the difference between an actual read-write pointer differential and a target differential. In a master unit, the target differential is a predetermined target value corresponding to a desired delay in the buffer. The actual pointer differential of the master unit is passed to one or more slave units. The actual pointer differential of the master unit is used as the target differential of the slave units. The pointer differentials of the slave units are thereby driven to track the pointer differential of the master unit, keeping the units synchronized.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: A low delay corrector (LDC) unit includes a non-linear function generator and a filter. The nonlinear function generator receives a first signal and outputs a second signal in dependence on the first signal and a transfer function of the nonlinear function generator. The filter is fed in dependence on the second signal output by the nonlinear function generator. The first signal received by the nonlinear function generator is derived in dependence on an input signal provided to an input of the LDC unit and an output of the filter. An output of the LDC unit is derived in dependence on the first signal received by the nonlinear function generator and the second signal output by the nonlinear function generator.

Abstract: Systems and methods for synchronizing multiple digital audio controller chips, wherein one of the chips is designated as a master and the other chips are designated as slaves. A common line connects all of the chips and is used to transmit synchronization signals from the master to the slaves. Each of the chips listens for an appropriate signal and, when the signal is detected, all of the chips simultaneously begin operation. In one embodiment, the synchronization signal comprises a transition on the shared line to an active state. The transition is repeated at fixed intervals and maintained in the active state for a fixed period in order to enable the chips to determine whether synchronization is being maintained. The signal may be sampled and/or filtered to improve reliability. The chips may be able to drive the shared line active to indicate that synchronization has been lost.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: Systems and methods are provided for converting input data streams having variable input sample rates to an output sample rate, which systems and methods are used in processing the data streams. In one embodiment, a system includes a clock source, a counter configured to count cycles for a corresponding data stream, and a data processor. The data processor is configured to read the number of cycles counted by the counter between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted.

Abstract: Systems and methods for improving the stability of feedback and/or feed-forward subsystems in digital amplifiers. One embodiment comprises a digital pulse width modulation (PWM) controller. The controller includes an input for receiving a digital audio input signal and is configured to generate a PWM output signal based on the input signal at an output. The controller also has control inputs for receiving external audio correction signals such as feedback and power supply feed-forward signals. The controller has correction circuitry for processing the received external control signals and modifying the input signal based on these signals. Fault detectors monitor fault conditions at various locations within the correction circuitry, and a protection control unit receives fault signals from the fault detectors and modifies operation of the controller in response to the fault signals.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: Systems and methods for minimizing performance degradation due to component mismatch in the feedback path of a digital PWM amplifier feedback loop. One embodiment comprises a digital pulse width modulated (PWM) amplifier with feedback. The amplification subsystem receives a digital audio signal and produces an analog output signal. The feedback loop produces a feedback signal based on the filtered analog output signal and modifies the digital audio signal based on the feedback signal. The feedback loop includes a filter configured to filter the analog output signal and correction circuitry configured to correct component mismatch errors introduced by the filter. In one embodiment, the correction circuitry receives a measurement of a power supply voltage, multiplies the measured voltage by a gain and adds the scaled measurement to the feedback signal to correct for the component mismatch errors.

Abstract: Systems and methods for using multiple rate estimate counters in converting input data streams having variable sample rates to an output sample rate that are used in processing the data streams. In one embodiment, a system includes a clock source, first and second counters coupled to the clock source and configured to count cycles for corresponding data streams, and a data processor coupled to the first and second counters. The data processor is configured to read the number of cycles counted by each of the counters between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted, and to convert the second data stream to the predetermined output sample rate based on the ratio of the numbers of cycles counted in the first and second counters.

Abstract: Systems and methods for minimizing performance degradation due to component mismatch in the feedback path of a digital PWM amplifier feedback loop. One embodiment comprises a digital pulse width modulated (PWM) amplifier with feedback. The amplification subsystem receives a digital audio signal and produces an analog output signal. The feedback loop produces a feedback signal based on the filtered analog output signal and modifies the digital audio signal based on the feedback signal. The feedback loop includes a filter configured to filter the analog output signal and correction circuitry configured to correct component mismatch errors introduced by the filter. In one embodiment, the correction circuitry receives a measurement of a power supply voltage, multiplies the measured voltage by a gain and adds the scaled measurement to the feedback signal to correct for the component mismatch errors.

Abstract: Systems and methods for minimizing errors due to component variation in switching amplifiers utilizing power supply feed forward techniques. One embodiment comprises a digital PWM amplifier having an amplification subsystem for receiving a digital audio signal and producing an analog output signal. The amplifier includes a power supply feed-forward path configured to modify the digital audio signal based on a power supply measurement. The feed-forward path includes an analog filter configured to filter the power supply measurement, as well as correction circuitry configured to correct component mismatch errors introduced by the filter. The power supply measurement may be a power supply difference, a power supply common mode, or both. In either case, the power supply measurement is corrected by multiplying the measurement by an appropriately scaled power supply difference.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using simulation-based feedback. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a simulator configured to model processing of audio signals by the plant. The outputs of the plant and the simulator are provided to a subtractor, the output of which is then added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal for input to the subtractor. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.

Abstract: Systems and methods for over-current protection in all-digital amplifiers using low-cost current sensing mechanisms. An over-current hard clipping unit receives a digital audio signal, clips the signal according to a clip level, and provides the signal to a modulator. The modulator modulates the signal to produce, e.g., a PWM signal and provides the modulated signal to an output stage which generates an output current to drive a speaker. An over-current sensing unit is compares the output current to a threshold value and generates a binary signal indicating whether the output current exceeds the threshold value. The hard clipping unit receives the binary signal and ramps down the clip level during time periods in which the binary signal indicates that the output current exceeds the threshold. When the binary signal indicates that the output current does not exceed the threshold value, the hard clipping unit ramps up the clip level.