Abstract: Systems and methods for over-current protection in all-digital amplifiers using low-cost current sensing mechanisms. An over-current hard clipping unit receives a digital audio signal, clips the signal according to a clip level, and provides the signal to a modulator. The modulator modulates the signal to produce, e.g., a PWM signal and provides the modulated signal to an output stage which generates an output current to drive a speaker. An over-current sensing unit is compares the output current to a threshold value and generates a binary signal indicating whether the output current exceeds the threshold value. The hard clipping unit receives the binary signal and ramps down the clip level during time periods in which the binary signal indicates that the output current exceeds the threshold. When the binary signal indicates that the output current does not exceed the threshold value, the hard clipping unit ramps up the clip level.

Abstract: Systems and methods for minimizing errors due to component variation in switching amplifiers utilizing power supply feed forward techniques. One embodiment comprises a digital PWM amplifier having an amplification subsystem for receiving a digital audio signal and producing an analog output signal. The amplifier includes a power supply feed-forward path configured to modify the digital audio signal based on a power supply measurement. The feed-forward path includes an analog filter configured to filter the power supply measurement, as well as correction circuitry configured to correct component mismatch errors introduced by the filter. The power supply measurement may be a power supply difference, a power supply common mode, or both. In either case, the power supply measurement is corrected by multiplying the measurement by an appropriately scaled power supply difference.

Abstract: Systems and methods for improving the stability of feedback and/or feed-forward subsystems in digital amplifiers. One embodiment comprises a digital pulse width modulation (PWM) controller. The controller includes an input for receiving a digital audio input signal and is configured to generate a PWM output signal based on the input signal at an output. The controller also has control inputs for receiving external audio correction signals such as feedback and power supply feed-forward signals. The controller has correction circuitry for processing the received external control signals and modifying the input signal based on these signals. Fault detectors monitor fault conditions at various locations within the correction circuitry, and a protection control unit receives fault signals from the fault detectors and modifies operation of the controller in response to the fault signals.

Abstract: Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.

Abstract: Systems and methods for synchronizing multiple digital audio controller chips, wherein one of the chips is designated as a master and the other chips are designated as slaves. A common line connects all of the chips and is used to transmit synchronization signals from the master to the slaves. Each of the chips listens for an appropriate signal and, when the signal is detected, all of the chips simultaneously begin operation. In one embodiment, the synchronization signal comprises a transition on the shared line to an active state. The transition is repeated at fixed intervals and maintained in the active state for a fixed period in order to enable the chips to determine whether synchronization is being maintained. The signal may be sampled and/or filtered to improve reliability. The chips may be able to drive the shared line active to indicate that synchronization has been lost.

Abstract: Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.