Patents by Inventor Daniel Shepard
Daniel Shepard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11926630Abstract: This application relates to compounds of Formula (I): or pharmaceutically acceptable salts thereof, which are inhibitors of PI3K-? which are useful for the treatment of disorders such as autoimmune diseases, cancer, cardiovascular diseases, and neurodegenerative diseases.Type: GrantFiled: November 30, 2021Date of Patent: March 12, 2024Assignee: Incyte CorporationInventors: Brent Douty, Andrew W. Buesking, David M. Burns, Andrew P. Combs, Nikoo Falahatpisheh, Ravi Kumar Jalluri, Daniel Levy, Padmaja Polam, Lixin Shao, Stacey Shepard, Artem Shvartsbart, Richard B. Sparks, Eddy W. Yue
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Patent number: 11067350Abstract: This invention discloses embodiments which disclose a handgun frame conversion and adapter system which provides for the conversion of use of a handgun frame from use with a first slide to use with a second and dissimilar slide (such as allowing a Glock® Gen 1, Gen 2 or Gen 3 slide to be used on a Gen 4 or Gen 5 Glock® compatible frame). Aspects of this frame conversion system include a conversion adapter which is installable and removable from the frame portion of the handgun, thereby allowing any one of a number of handgun slides to be mounted or installed on one frame.Type: GrantFiled: October 30, 2019Date of Patent: July 20, 2021Assignee: Lone Wolf Distributors, Inc.Inventors: Daniel Shepard, Jr., Robert Hansel, Zachary Carlson, Daniel Shepard, III, Matthew Vernon
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Publication number: 20180004264Abstract: To provide enhanced power distribution in integrated circuits, solid state memory arrays, or other solid state devices, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, an integrated circuit power distribution system is provided. The system includes a first power distribution bus coupled to a current source and a threshold bridge element, and a second power distribution bus coupled to one or more target devices and the threshold bridge element. The threshold bridge element comprises a bridge material with properties that pass current responsive to application of a threshold voltage across the bridge material.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Mac D. Apodaca, Daniel Bedau, Daniel Shepard
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Publication number: 20160327653Abstract: An apparatus including a global navigation satellite system (GNSS) antenna, a mobile GNSS receiver connected to the GNSS antenna, a camera operable to produce an image, and a processor communicably coupled to the mobile GNSS receiver and the camera. The mobile GNSS receiver is operable to produce a set of carrier-phase measurements from a GNSS. The processor is operable to receive the image and the set of carrier-phase measurements, extract point feature measurements from the image, model the point feature measurements based on the image to produce a point feature model, model the set of carrier-phase measurements to produce a carrier-phase model, execute a cost function including the point feature measurements, the carrier-phase measurements, the point feature model, and the carrier-phase model, and determine a state associated with the apparatus based on the executed cost function.Type: ApplicationFiled: July 15, 2016Publication date: November 10, 2016Inventors: Todd Humphreys, Kenneth Pesyna, JR., Daniel Shepard
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Publication number: 20140257799Abstract: The present invention is a means to provide a user interface that will naturally cause a person to speak at a normal talking volume. It is based on a mechanism whereby the user's speech is compared to a threshold to determine if the user is speaking too loudly and provides feedback to the user. This mechanism could be incorporated into a headset, a cell phone, a smartphone, or into other communication devices. It is useful for operation with or without a headset.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Inventor: Daniel Shepard
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Patent number: 8526217Abstract: An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.Type: GrantFiled: December 3, 2012Date of Patent: September 3, 2013Assignee: Contour Semiconductor, Inc.Inventor: Daniel Shepard
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Publication number: 20130114328Abstract: An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.Type: ApplicationFiled: December 3, 2012Publication date: May 9, 2013Inventor: Daniel Shepard
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Publication number: 20080072421Abstract: The present invention is a means for forming substrates for the fabrication of active devices using topography based lithographic manufacturing techniques. A form is used to create a substrate by injection molding, embossing, or by other means of applying a topography to the substrate using a form. This substrate can be plastic, glass or other moldable material or a moldable material layer on another material, but is typically an insulating material that will not participate in the operation of the end devices. The present invention is a means for creating such a form. Furthermore, the present invention is also a means for molding the backside of said substrate, either simultaneously or in multiple steps, such that active devices or portions of a given active device can be formed on both front and back sides of the substrate. The present invention includes means for interconnecting components on both sides of the substrate.Type: ApplicationFiled: November 13, 2007Publication date: March 27, 2008Inventor: Daniel Shepard
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Publication number: 20080013354Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.Type: ApplicationFiled: July 20, 2007Publication date: January 17, 2008Applicant: Contour Semiconductor, Inc.Inventor: Daniel Shepard
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Publication number: 20080013398Abstract: A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.Type: ApplicationFiled: July 19, 2007Publication date: January 17, 2008Applicant: Contour Semiconductor, Inc.Inventor: Daniel Shepard
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Publication number: 20080016414Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.Type: ApplicationFiled: July 20, 2007Publication date: January 17, 2008Applicant: Contour Semiconductor, Inc.Inventor: Daniel Shepard
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Publication number: 20070247890Abstract: The scale of the devices in a diode array storage device, and their cost, are reduced by changing the semiconductor based diodes in the storage array to cold cathode, field emitter based devices. The field emitters and a field emitter array may be fabricated utilizing a topography-based lithographic technique.Type: ApplicationFiled: February 15, 2007Publication date: October 25, 2007Inventor: Daniel Shepard
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Publication number: 20070117388Abstract: Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked layers having desired electrical characteristics is applied to the substrate and planarized in a manner that creates electrical devices and connections therebetween. The microelectronic devices can include a series of row and columns and are used to store data at their intersection.Type: ApplicationFiled: January 19, 2007Publication date: May 24, 2007Applicant: Contour Semiconductor, Inc.Inventor: Daniel Shepard
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Publication number: 20070028150Abstract: As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory manufacturing costs are significant and will grow as the capacity of the devices grows—the higher the memory's capacity, the more storage locations that must be tested, and the longer the testing operation will take. The cost of the testing can be calculated by dividing the amortized cost of the test equipment by the number of devices tested. As memory devices enter the Gigabyte range and larger, the number of devices that can be tested by a given piece of test equipment will go down. As a result, the cost per unit attributable to testing will rise.Type: ApplicationFiled: September 29, 2006Publication date: February 1, 2007Applicant: Contour Semiconductor, Inc.Inventor: Daniel Shepard
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Publication number: 20060166508Abstract: The present invention is a method of applying a topographical surface to a part such as a substrate without the need for low temperature softening of that part while retaining high aspect ratios and densely packed features in that topography. A substrate, selected for its ability to be processed at a given desired temperature, has a layer of material applied to its surface. This layer is selected, among other reasons, for its ability to be molded. Typically, it is expected that the substrate will be able to withstand the higher temperatures of semiconductor post-processing whereas the applied layer will be moldable at low temperatures. This combination enables low cost embossing of a topography into this surface layer. The present invention comprises means to transfer this topography from the low temperature material into the higher temperature substrate.Type: ApplicationFiled: January 27, 2006Publication date: July 27, 2006Inventor: Daniel Shepard
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Publication number: 20060013029Abstract: The present invention is a means for constructing a high density memory device for very low cost by fabricating the device three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers—not the exponentially greater number of decoded rows and columns. Furthermore, to keep the testing of the device low in cost, a row and column interconnect means is disclosed for testing the any two-dimensional array within the three-dimensional array with a single continuity and short-circuit test.Type: ApplicationFiled: September 19, 2005Publication date: January 19, 2006Applicant: Contour SemiconductorInventor: Daniel Shepard
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Publication number: 20050245069Abstract: The present invention relates to the manufacture and processing of semiconductor wafers, and more particularly to methods for keeping the surface of a wafer flat during processing to improve lithography, planarization, and other process steps that benefit from a flatter wafer. The present invention is a means to disrupt the long-range stress across the surface of a wafer made of crystalline silicon or other materials so as to prevent distortions such as dishing of that wafer. To prevent such dishing or similar distortions, the long-range continuity of the film must be disrupted. The long-range continuity of the film can be disrupted simply by etching channels in the surface of the wafer. These etched channels could be incorporated into or combined with registration marks that might be etched initially on the wafer for the purpose of enabling a step and repeat lithography exposure tool to find each exposure point.Type: ApplicationFiled: April 28, 2005Publication date: November 3, 2005Inventor: Daniel Shepard
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Publication number: 20050067675Abstract: The present invention is a means for forming substrates for the fabrication of active devices using topography based lithographic manufacturing techniques. A form is used to create a substrate by injection molding, embossing, or by other means of applying a topography to the substrate using a form. This substrate can be plastic, glass or other moldable material or a moldable material layer on another material, but is typically an insulating material that will not participate in the operation of the end devices. The present invention is a means for creating such a form. Furthermore, the present invention is also a means for molding the backside of said substrate, either simultaneously or in multiple steps, such that active devices or portions of a given active device can be formed on both front and back sides of the substrate. The present invention includes means for interconnecting components on both sides of the substrate.Type: ApplicationFiled: August 19, 2004Publication date: March 31, 2005Inventor: Daniel Shepard
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Patent number: D886935Type: GrantFiled: October 31, 2018Date of Patent: June 9, 2020Assignee: Lone Wolf Distributors, Inc.Inventors: Daniel Shepard, Jr., Robert Hansel, Zachary Carlson, Daniel Shepard, III, Matthew Vernon
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Patent number: D972678Type: GrantFiled: October 30, 2019Date of Patent: December 13, 2022Assignee: Lone Wolf Distributors, Inc.Inventors: Daniel Shepard, Jr., Robert Hansel, Zachary Carlson, Daniel Shepard, III, Matthew Vernon