Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.

Abstract: An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transistor, and a second pre-buffer to drive the NMOS transistor. Each output buffer receives power from a pre-buffer supply filtering circuit, which may include a supply capacitor for stabilizing supply voltage, a low-pass first pre-buffer supply filter to filter the voltage supplied to the first pre-buffer, and a low-pass second pre-buffer supply filter the voltage supplied to the second pre-buffer.

Abstract: Methods, systems, and devices for digit line management for a memory array are described. A memory array may include a plate that is common to a plurality of memory cells. Each memory cell associated with the common plate may be coupled with a respective digit line. One or more memory cells common to the plate may be accessed by concurrently selecting the plate and each digit line associated with the plate. Concurrent selection of all digit lines associated with the plate may be supported by shield lines between the selected digit lines. Additionally or alternatively, selection of all digit lines associated with the plate may be supported by improved sensing schemes and related amplifier configurations.

Abstract: Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.

Abstract: The present disclosure includes apparatuses, methods, and systems for current separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell having a ferroelectric material, and determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell and the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, systems, and devices for deck selection layouts in a memory device are described. In some implementations, a tile of a memory array may be associated with a level above a substrate, and may include a set of memory cells, a set of digit lines, and a set of word lines. Selection transistors associated with a tile of memory cells may be operable for coupling digit lines of the tile with circuitry outside the tile, and may be activated by various configurations of one or more access lines, where the various configurations may be implemented to trade off or otherwise support design and performance characteristics such as power consumption, layout complexity, operational complexity, and other characteristics. Such techniques may be implemented for other aspects of tile operations, including memory cell shunting or equalization, tile selection using transistors of a different level, or signal development, or various combinations thereof.

Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

Abstract: Methods, systems, and devices for deck-level signal development cascodes are described. A memory device may include transistors that support both a signal development and decoding functionality. In a first operating condition (e.g., an open-circuit condition), a transistor may be operable to isolate first and second portions of an access line based on a first voltage applied to a gate of the transistor. In a second operating condition (e.g., a signal development condition), the transistor may be operable to couple the first and second portions of the access line and generate an access signal based on a second voltage applied to the gate of the transistor. In a third operating condition (e.g., a closed-circuit condition), the transistor may be operable to couple the first and second portions of the access line based on applying a third voltage greater than the second voltage to the gate of the transistor.

Abstract: Field-effect transistors, and integrated circuit devices containing such field-effect transistors, might include a semiconductor material having a first conductivity type, a first source/drain region having a second conductivity type, a second source/drain region having the second conductivity type, a first contact connected to the first source/drain region, a conductor overlying an active area of the semiconductor material and having an annular portion surrounding the first contact and a spur portion extending from an outer perimeter of the annular portion of the conductor, a second contact connected to the second source/drain region outside the annular portion of the conductor, a dielectric between the conductor and the active area, and a third contact overlying the active area and connected to the spur portion of the conductor.

Abstract: Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, systems, and devices for differential amplifier schemes for non-switching state compensation are described. During a read operation, a first node of a memory cell may be coupled with an input of differential amplifier while a second node of the memory cell may be biased with a first voltage (e.g., to apply a first read voltage across the memory cell). The second node of the memory cell may subsequently be biased with a second voltage (e.g., to apply a second read voltage across the memory cell), which may support the differential amplifier operating in a manner that compensates for a non-switching state of the memory cell. By compensating for a non-switching state of a memory cell during read operations, read margins may be increased.

Abstract: Apparatuses, systems, and methods for ferroelectric memory (FeRAM) cell operation. An FeRAM cell may have different charge regions it can operate across. Some regions, such as dielectric regions, may operate faster, but with reduced signal on a coupled digit line. To improve the performance while maintaining increased speed, two digit lines may be coupled to the same sense amplifier, so that the FeRAM cells coupled to both digit lines contribute signal to the sense amplifier. For example a first digit line in a first deck of the memory and a second digit line in a second deck of the memory may both be coupled to the sense amplifier. In some embodiments, additional digit lines may be used as shields (e.g., by coupling the shield digit lines to a ground voltage) to further improve the signal-to-noise ratio.

Abstract: Methods, systems, and devices for sensing techniques for differential memory cells are described. A method may include selecting a pair of memory cells that comprise a first memory cell coupled with a first digit line and a second memory cell coupled with a second digit line for a read operation, the pair of memory cells storing one bit of information. The method may further include applying a first voltage to a plate line coupled with the first memory cell and the second memory cell and applying a second voltage to a select line to couple the first digit line and the second digit line with a sense amplifier. The amplifier may sense a logic state of the pair of memory cells based on a difference between a third voltage of the first digit line and a fourth voltage of the second digit line.

Abstract: Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.