Abstract: Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.

Abstract: Methods, systems, and devices for memory operations are described. First scrambling sequences may be generated for first addresses of a memory device after an occurrence of a first event, where the first addresses may be associated with commands received at the memory device. Portions of the memory array corresponding to the first address may be accessed based on the first scrambling sequences. After an occurrence of a subsequent event, second scrambling sequences may be generated for the first addresses, where the second scrambling sequences may be different than the first set of scrambling sequences. After the occurrence of the subsequent event, the portions of the memory array may be accessed based on the second scrambling sequences.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, systems, and devices for low voltage ferroelectric memory cell sensing are described. As part of an access operation for a memory cell, gates of two cascodes may be biased to compensate for associated threshold voltages. An extracted signal corresponding to a charge stored in the memory cell may be transferred through a first cascode to charge a first capacitor. Similarly, a reference signal developed at a dummy digit line may be transferred through a second cascode to charge a second capacitor. By comparing the reference signal developed at the dummy digit line to the extracted signal from the memory cell, the effect of variations in memory cell performance on the sense window may be reduced. Additionally, based on biasing the gates of the cascodes, the difference between the signals compared at the sense component may be low compared to other sensing schemes.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Apparatuses and techniques for compensating for noise, such as a leakage current, in a memory array are described. Leakage currents may, for example, be introduced onto a digit line from unselected memory cells. In some cases, a compensation component may be coupled with the digit line during a first phase of a read operation, before the target memory cell has been coupled with the digit line. The compensation component may sample a current on the digit line and store a representation of the sampled current. During a second phase of the read operation, the target memory cell may be coupled with the digit line. During the second phase, the compensation component may compensate for leakage or other parasitic effects by outputting a current on the digit line during the read operation based on the stored representation of the sampled current.

Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

Abstract: Apparatuses, systems, and methods for ferroelectric memory (FeRAM) cell operation. An FeRAM cell may have different charge regions it can operate across. Some regions, such as dielectric regions, may operate faster, but with reduced signal on a coupled digit line. To improve the performance while maintaining increased speed, two digit lines may be coupled to the same sense amplifier, so that the FeRAM cells coupled to both digit lines contribute signal to the sense amplifier. For example a first digit line in a first deck of the memory and a second digit line in a second deck of the memory may both be coupled to the sense amplifier. In some embodiments, additional digit lines may be used as shields (e.g., by coupling the shield digit lines to a ground voltage) to further improve the signal-to-noise ratio.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.

Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory tell based at least in part on the sense signal.

Abstract: Memory cells are described that include two reference voltages that may store and sense three distinct memory states by compensating for undesired intrinsic charges affecting a memory cell. Although embodiments described herein refer to three memory states, it should be appreciated that in other embodiments, the memory cell may store or sense more than three charge distributions using the described methods and techniques. In a first memory state, a programming voltage or a sensed voltage may be higher than a first reference voltage and a second reference voltage. In a second memory state, the applied voltage or the sensed voltage may be between the first and the second reference voltages. In a third memory state, the applied voltage or the sensed voltage may be lower than the first and the second reference voltages. As such, the memory cell may store and retrieve three memory states.

Abstract: Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor may be coupled with the first digit line and a sense component common to a set of digit lines and a set of select lines. A second select line may be coupled with the third transistor and configured to couple the sense component with the first digit line and to couple the sense component with a second digit line. The sense component may determine a logic state stored by the memory cell based on the signal from the first digit line and the signal from the second digit line.

Abstract: Methods, systems, and apparatuses for self-referencing memory cells are described. A reference value for a cell may be created through multiple sense operations on the cell. The cell may be sensed several times and an average of at least two sensing operations may be used as a reference for another sense operation. For example, the cell may be sensed and the resulting charge stored at a capacitor. The cell may be biased to one state, sensed a second time, and the resulting charge stored at another capacitor. The cell may be biased to another state, sensed a third time, and the resulting charge stored to another capacitor. The values from the second and third sensing operations may be averaged and used as a reference value in a comparison with value of the first sensing operation to determine a logic state of the cell.

Abstract: Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.

Abstract: A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. Virtually grounding the digit line may be achieved by activating a switching component (e.g., a p-type field-effect transistor) that is electronic communication with the digit line. The charge of the ferroelectric capacitor may be transferred through the switching component. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

Abstract: Methods and apparatus for sensing a memory cell using lower offset, higher speed sense amplifiers are described. A sense amplifier may include an amplifier component that is configurable to operate in an amplifier mode or a latch mode. In some examples, the amplifier component may be configured to operate in the amplifier or latch mode by activating or deactivating switching components inside the amplifier component. When configured to operate in the amplifier mode, the amplifier component may be used, during a read operation of a memory cell, to pre-charge a digit line and/or amplify a signal received from the memory cell. When configured to operate in the latch mode, the amplifier component may be used to latch a state of the memory cell. In some cases, the amplifier component may use some of the same internal circuitry for pre-charging the digit line, amplifying the signal, and/or latching the state.

Abstract: An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transistor, and a second pre-buffer to drive the NMOS transistor. Each output buffer receives power from a pre-buffer supply filtering circuit, which may include a supply capacitor for stabilizing supply voltage, a low-pass first pre-buffer supply filter to filter the voltage supplied to the first pre-buffer, and a low-pass second pre-buffer supply filter the voltage supplied to the second pre-buffer.