Abstract: A method, system, and product in a data processing system are disclosed for testing a switched area network device having a standardized serial fabric interconnect and that includes logic modules. The device includes test mode logic. A test command is received within the test mode logic via the standardized serial fabric interconnect from an external tester. The test command is then executed by the test mode logic, and a result of the test is then transmitted to the tester via the standardized serial fabric interconnect.

Abstract: A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.

Abstract: A method and implementing system is provided in which multiple nodes of a Peripheral Component Interconnect PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method and implementing computer system are provided which allows for significantly improved input/output (I/O) subsystem designs in all systems which include serialized I/O transactions such as so-called Express specification systems. Transaction control methodology is implemented to improve Express design requirements for Express devices such as an Express switch, Express-PCI bridge, endpoint, and root complex. This is accomplished by utilizing improved transaction ordering and state machine and corresponding buffer design and improved flow control credit methodology which enables improved processing for controlling transactions flowing through Express devices including Express switches and Express-PCI bridges. An Express-PCI/PCIX transition bridge design is also provided, along with the flow control credit methodology and implementation within the Express-PCI/PCIX bridge design to enable efficient interfacing between Express and legacy or existing PCI/PCIX systems.

Abstract: A method and implementing computer system are provided which allows for significantly improved input/output (I/O) subsystem designs in all systems which include serialized I/O transactions such as so-called Express specification systems. Transaction control methodology is implemented to improve Express design requirements for Express devices such as an Express switch, Express-PCI bridge, endpoint, and root complex. This is accomplished by utilizing improved transaction ordering and state machine and corresponding buffer design and improved flow control credit methodology which enables improved processing for controlling transactions flowing through Express devices including Express switches and Express-PCI bridges. An Express-PCI/PCIX transition bridge design is also provided, along with the flow control credit methodology and implementation within the Express-PCI/PCIX bridge design to enable efficient interfacing between Express and legacy or existing PCI/PCIX systems.

Abstract: A method and implementing computer system are provided which allows for significantly improved input/output (I/O) subsystem designs in all systems which include serialized I/O transactions such as so-called Express specification systems. Transaction control methodology is implemented to improve Express design requirements for Express devices such as an Express switch, Express-PCI bridge, endpoint, and root complex. This is accomplished by utilizing improved transaction ordering and state machine and corresponding buffer design and improved flow control credit methodology which enables improved processing for controlling transactions flowing through Express devices including Express switches and Express-PCI bridges. An Express-PCI/PCIX transition bridge design is also provided, along with the flow control credit methodology and implementation within the Express-PCI/PCIX bridge design to enable efficient interfacing between Express and legacy or existing PCI/PCIX systems.

Abstract: A method and apparatus for preventing unauthorized access to data stored in memory utilizing two programmable logic devices as front end interfaces for the memory device and the data processing device which is to utilize the memory device, respectively. The two programmable logic devices are complementary programmed such that the signal lines between the data processing device and the memory core and/or their timing are scrambled at the interface between the two programmable logic devices, but are properly ordered with the proper timing at the interface between the memory core and the first programmable logic device and the interface between the data processing device and the second programmable logic device.

Abstract: A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to transmitting data between the end nodes. An instance number is associated with this particular logical connection. The instance number is included in each packet transmitted between the end nodes while this logical connection remains established. The instance number remains constant during this logical connection. The instance number is altered, such as by incrementing it, each time a logical connection between these end nodes is reestablished. Thus, each packet is associated with a particular instance of the logical connection. When a packet is received, the instance number included in the packet may be used to determine whether the packet is a stale packet transmitted during a previous logical connection between these end nodes.

Abstract: A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which is accessed by adapters and adapter bridge circuits which are normally outside of the system coherency domain. An extended architecture includes one or more host bridges. At least one of the host bridges is coupled to I/O adapter devices through a lower-level bus-to-bus bridge and one or more I/O busses. The host bridge maintains a buffer coherency directory and when Invalidate commands are received by the host bridge, the bridge buffers containing the referenced data are identified and the indicated data are invalidated.

Abstract: An improved handheld merchandise scanning device and method are disclosed. A first and second mode are enabled in the scanning device for scanning a product tag which includes product information and a security tag. The product tag is scanned utilizing the scanning device in the first mode to obtain the product information without deactivating the security tag. The product tag is scanned utilizing the scanning device in the second mode to concurrently obtain the product information and deactivate the security tag.

Abstract: A system and method for optimally processing split request transactions across a PCI-X bridge with a PCI-X bridge buffer. The split transaction mode of the PCI-X bridge buffer is toggled between a No Over-commit mode and an over-commit mode. Over-commitment of the buffer is inhibited when the split transaction mode is toggled to the No Over-commit mode and when the buffer is over committed by the bridge. At least some over-commitment of the buffer is allowed by the bridge when the split transaction mode is toggled to the over-commit mode and when the buffer is not over committed by the bridge. The over-commit mode may be an Over-commitment mode or a Flood mode. The Over-commitment mode allows some degree of over commitment of the buffer by the bridge while the Flood mode allows the bridge to forward all split request transactions regardless of size of the transactions or amount of available space in the buffer when the Over-commit mode is in a Flood mode.

Abstract: A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.

Abstract: An open format storage subsystem and method are provided. The storage subsystem and method include at least one host endnode, at least one processing unit endnode, and at least one storage endnode. These endnodes are partitioned according to partition tables assigned to the ports of the endnodes and partition keys assigned to queue pairs of the ports. Based on these partition keys, partitions in the storage subsystem are designated. In this way, certain endnodes may be designated as being able to communicate with only certain other ones of the endnodes. Because of the partitioning mechanism of the present invention, an open format storage subsystem is formulated such that the types of endnodes in the storage subsystem are not limited to vendor specific units. This enhances the ability to add and remove units from the storage subsystem by removing the limitations typically found in closed storage subsystems.

Abstract: An apparatus and method for an advanced multiplexing technique to allow a single host to support multiple Internet Protocol (IP) queue pairs with little or no overhead are provided. With the apparatus and method, after a queue pair is created, Internet Protocol filter attributes and values are set up for the queue pair through value added features to the standard InfiniBand “QP Modify” method. The IP filters are used during normal operations to determine which queue pair is associated with an incoming packet. During normal operations, when a channel adapter receives an Internet Protocol (IP) over InfiniBand (IB) packet, it uses one or more of several fields in the packet's transport and/or network header to determine which queue pair shall receive the packet. Thus, the host channel adapter uses the IP filters to route incoming packets to the appropriate queue pair and thereby allow more than one queue pair to be used to support IP.

Abstract: A method and apparatus for preventing unauthorized access to data stored in memory utilizing two programmable logic devices as front end interfaces for the memory device and the data processing device which is to utilize the memory device, respectively. The two programmable logic devices are complementary programmed such that the signal lines between the data processing device and the memory core and/or their timing are scrambled at the interface between the two programmable logic devices, but are properly ordered with the proper timing at the interface between the memory core and the first programmable logic device and the interface between the data processing device and the second programmable logic device.

Abstract: An apparatus and method for virtualizing a queue pair space to minimize time-wait impacts. The apparatus and method allocate virtual queue pairs from a virtual queue pair pool of a node to connections between the node and other nodes. The connection is established between a physical queue pair of the node and physical queue pairs of other nodes. However, from the viewpoint of the other nodes, they are communicating with the present node using the virtual queue pair and not the physical queue pair for the present node. By using the virtual queue pairs, the same physical queue pair may accommodate multiple connections with other nodes simultaneously. Moreover, by using a virtual queue pair rather than a physical queue pair, when a connection is torn down, the virtual queue pair is placed in a time-wait state rather than the physical queue pair. As a result, the physical queue pair may continue to function while the virtual queue pair is in the time-wait state.

Abstract: A method and implementing computer system is provided in which specific device identification information is acquired when a faulty condition is detected during an information transfer transaction, and the condition is reported to the device driver of the identified device for corrective action without initiating a system shut-down. In one example, PCI adapter sequence information, including tag number, requester bus number, requester device number and requester function number is captured and used in reporting an error condition in order to identify and isolate the adapter in a recovery operation.

Abstract: A method for determining parameters needed to communicate with a remote node in a computer network is provided. The invention comprises determining the location of the remote node to which an InfiniBand (IB) node might desire to communicate. This resolution comprises determining the location of the remote node based on a desired application or service, and then determining the IB parameters needed to communicate with the remote node. The resolution might also involve determining the specific queue pairs that associated with the service dynamically. The general solution is applied to IP service resolution.

Abstract: The invention provides an apparatus and method of allowing a device to respond to a configuration query only if it is the true target of the query. In one embodiment of the invention, logic gates having two inputs are provided. The first input of the logic gates is connected to the signal of a bridge that selects a device when the address of the signal is referenced in the configuration query. The second input of the logic gate receives a signal indicating whether the local bus or the subordinate bus is being configured and the output of the logic gate is used to enable the device. In a second embodiment, certain signals designated to indicate the selection of a bus are used to enable devices to respond to configuration queries.

Abstract: A system and method for establishing multiple connections using a private data field of a communication management protocol is provided. With the present invention, a Service ID identifies a specific consumer and the private data field contains a list of connection attributes for each connection that is to be established. An active side requests a connection and the passive side replies to the connection request. The active side sends the passive side a connection establishment request. This connection establishment request includes a Service ID which identifies a passive side process associated with a service. This connection establishment request also includes communication attributes of one or more connected services and datagram services associated with the Service ID. The passive passes the connection request to a process associated with the service. If the passive side process does not wish to carry out the service, a negative reply message is returned to the active side.