Patents by Inventor Darrell Rinerson
Darrell Rinerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8395928Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.Type: GrantFiled: August 9, 2011Date of Patent: March 12, 2013Assignee: Unity Semiconductor CorporationInventors: Julie Casperson Brewer, Christophe Chevallier, Wayne Kinney, Roy Lambertson, Darrell Rinerson, Lawrence Schloss
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Publication number: 20130059436Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.Type: ApplicationFiled: October 31, 2012Publication date: March 7, 2013Inventors: Darrell Rinerson, Robin Cheung
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Publication number: 20120307542Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: ApplicationFiled: August 17, 2012Publication date: December 6, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Namala
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Publication number: 20120292585Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.Type: ApplicationFiled: August 3, 2012Publication date: November 22, 2012Applicant: Unity Semiconductor CorporationInventors: Robin Cheung, Darrell Rinerson, Travis Byonghyop Oh, Jon Bornstein, David Hansen
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Patent number: 8314024Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.Type: GrantFiled: May 15, 2009Date of Patent: November 20, 2012Assignee: Unity Semiconductor CorporationInventors: Darrell Rinerson, Robin Cheung
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Patent number: 8268667Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).Type: GrantFiled: August 23, 2011Date of Patent: September 18, 2012Assignee: Unity Semiconductor CorporationInventors: Darrell Rinerson, Robin Cheung, David Hansen, Steven Longcor, Rene Meyer, Jonathan Bornstein, Lawrence Schloss
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Patent number: 8270193Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: GrantFiled: January 29, 2010Date of Patent: September 18, 2012Assignee: Unity Semiconductor CorporationInventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
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Patent number: 8237142Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.Type: GrantFiled: March 1, 2011Date of Patent: August 7, 2012Assignee: Unity Semiconductor CorporationInventors: Robin Cheung, Jonathan Bornstein, David Hansen, Travis Byonghyop Oh, Darrell Rinerson
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Publication number: 20120087174Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.Type: ApplicationFiled: December 16, 2011Publication date: April 12, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: DARRELL RINERSON, CHRISTOPHE J. CHEVALLIER, WAYNE KINNEY, ROY LAMBERTSON, STEVEN W. LONGCOR, JOHN E. SANCHEZ, JR., LAWRENCE SCHLOSS, PHILIP F.S. SWAB, EDMOND WARD
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Publication number: 20120075914Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.Type: ApplicationFiled: October 4, 2011Publication date: March 29, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: BRUCE BATEMAN, DARRELL RINERSON, CHRISTOPHE CHEVALLIER, CHANG HUA SIAU
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Publication number: 20120064691Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: DARRELL RINERSON, WAYNE KINNEY, EDMOND R. WARD, STEVE KUO-REN HSIA, STEVEN W. LONGCOR, CHRISTOPHE J. CHEVALLIER, JOHN SANCHEZ, PHILIP F. S. SWAB
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Publication number: 20120033481Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.Type: ApplicationFiled: October 13, 2011Publication date: February 9, 2012Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: DARRELL RINERSON, WAYNE KINNEY, EDMOND R. WARD, STEVE KUO-REN HSIA, STEVEN LONGCOR, CHRISTOPHE J. CHEVALLIER, JOHN SANCHEZ, PHILIP F. S. SWAB
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Publication number: 20110315948Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).Type: ApplicationFiled: August 23, 2011Publication date: December 29, 2011Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: DARRELL RINERSON, JONATHAN BORNSTEIN, DAVID HANSEN, ROBIN CHEUNG, STEVEN W. LONGCOR, RENE MEYER, LAWRENCE SCHLOSS
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Publication number: 20110315943Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below un-etched conductive metal oxide layer(s), forming the un-etched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the un-etched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).Type: ApplicationFiled: September 2, 2011Publication date: December 29, 2011Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: DARRELL RINERSON, JONATHAN BORNSTEIN, DAVID HANSEN, ROBIN CHEUNG, STEVEN W. LONGCOR, RENE MEYER, LAWRENCE SCHLOSS
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Publication number: 20110291067Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.Type: ApplicationFiled: August 9, 2011Publication date: December 1, 2011Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: JULIE CASPERSON BREWER, DARRELL RINERSON, CHRISTOPHE J. CHEVALLIER, WAYNE KINNEY, ROY LAMBERTSON, LAWRENCE SCHLOSS
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Patent number: 8062942Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.Type: GrantFiled: June 30, 2008Date of Patent: November 22, 2011Inventors: Darrell Rinerson, Wayne Kinney, Edmond Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John E. Sanchez, Jr., Philip Swab
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Publication number: 20110278532Abstract: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.Type: ApplicationFiled: July 26, 2011Publication date: November 17, 2011Applicant: UNITY SEMICONDUCTOR CORPORATIONInventors: DARRELL RINERSON, CHRISTOPHE CHEVALLIER, WAYNE KINNEY, EDMOND WARD
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Patent number: 8031545Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.Type: GrantFiled: April 19, 2010Date of Patent: October 4, 2011Inventors: Darrell Rinerson, Christophe Chevallier, Chang Hua Siau
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Patent number: 8003511Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).Type: GrantFiled: December 18, 2009Date of Patent: August 23, 2011Inventors: Darrell Rinerson, Jonathan Bornstein, Robin Cheung, David Hansen, Steven W. Longcor, Rene Meyer, Lawrence Schloss
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Patent number: 7995371Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.Type: GrantFiled: July 26, 2007Date of Patent: August 9, 2011Inventors: Darrell Rinerson, Julie Casperson Brewer, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, Lawrence Schloss