Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

Abstract: A method of operating a semiconductor device can include providing a multi-bit count value to a temperature sensing circuit; and generating an output having a detect logic level from the temperature sensing circuit based on an internal temperature of the semiconductor device and the count value. In some embodiments, a semiconductor device can be a dynamic random access memory (DRAM) device.

Abstract: A method of operating a semiconductor device powered by a first power supply potential can include generating a first voltage signal having a first logic level in response to a voltage detector circuit detecting that the first power supply potential is essentially lower than a predetermined voltage; latching the first voltage signal to provide a first latched voltage signal; generating at least one read or write assist signal having a read or write assist enable logic level in response to the first latched voltage signal; and altering a read or write operation to a static random access memory (SRAM) cell in response to the at least one read or write assist signal having the read or write assist enable logic level as compared to when the at least one read or write assist signal has a read or write assist disable logic level.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A semiconductor device has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist disable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device when at an assist enable logic level as compared to the read or write operation when the assist signal has the assist disable logic level.

Abstract: A device can include a temperature circuit that can selectively set one of a plurality of temperature ranges. Each temperature range can have a temperature range upper limit value and a temperature range lower limit value. The temperature circuit can be disabled in response to a detection of a transition in a power supply voltage. In some embodiments, the temperature circuit can also be enabled a predetermined time period after the detection of the transition in the power supply voltage.

Abstract: A semiconductor device powered by a first power supply potential, can include a voltage detector circuit coupled to receive the first power supply potential and configured to provide at least one voltage window signal, the at least one voltage window signal indicating a predetermined voltage window in which the first power supply potential is located; an assist control circuit configured to provide at least one assist signal in response to the at least one voltage window signal; wherein the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell, as compared to the read or write operations without the at least one assist signal.

Abstract: A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. The first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate. The first capacitor node can be electrically connected to a first terminal, which is electrically connected to receive a power supply potential from a power supply terminal. The second semiconductor device can receive the power supply potential from the power supply terminal. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The first capacitor node includes at least one essentially vertically formed conductive portion disposed in the substrate of the first semiconductor device and through at least half of a vertical thickness of the first semiconductor device.

Abstract: A multi-chip stack can include a first semiconductor device disposed between a plurality of electrical connections and the second semiconductor device. The first semiconductor device can include a first through via and a first electrostatic discharge (ESD) protection circuit connected to a first one of the electrical connections. The first ESD Protection circuit can have a first ESD protection structure. The first through via provides an electrical connection through the first semiconductor device from a first surface to an opposite surface of the first semiconductor device and between the first one of the plurality of electrical connections and a first terminal of the first circuit. The first terminal of the first circuit can be free of an electrical connection to an ESD protection circuit having the first ESD protection structure formed on the second semiconductor device.

Abstract: A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, can include: generating at least one assist signal in the normal mode of operation wherein, when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal, and inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated.

Abstract: A method of providing a temperature value from a dynamic random access memory (DRAM) device can include receiving a test mode command that activates a temperature value output mode of operation; providing the temperature value to an output buffer circuit; providing an enable signal to the output buffer circuit; and outputting the temperature value that indicates a temperature range, the temperature value is outputted from the output buffer circuit to at least one terminal that is electrically connected external to the DRAM device; wherein the temperature value includes at least 5 binary bits.

Abstract: A semiconductor device has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist disable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device when at an assist enable logic level as compared to the read or write operation when the assist signal has the assist disable logic level.

Abstract: A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. A first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate, separated from one another by at least one capacitor dielectric. A first capacitor node can be electrically connected to the first terminal of the first capacitor. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The at least one essentially vertically formed conductive portion can comprise polysilicon.

Abstract: A system can include a first semiconductor device including a first capacitor with a first terminal coupled to receive a power supply potential; and a second semiconductor device including a first voltage generator coupled to the first terminal of the first capacitor, the first voltage generator provides a first voltage generator output potential at an output terminal. The first capacitor can include a first capacitor node and a second capacitor node, the first capacitor node and the second capacitor node each include at least one substantially vertically formed conductive portion in a substrate of the first semiconductor device that are separated from one another by at least one capacitor dielectric, the first capacitor node is electrically connected to the first terminal of the first capacitor.