Abstract: A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

Abstract: A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a temperature range having a temperature range upper limit value and a temperature range lower limit value. The temperature of the multi-chip package can be kept essentially within the temperature range for a predetermined time period by monitoring a thermal sensing element with a sensing circuit outside of the multi-chip package. The thermal sensing element may be located near the components with the lowest failure temperature to ensure the multi-chip package is not damaged during the healing process.

Abstract: A package can include first, second, and third dynamic random access memory (DRAM) semiconductor devices having first, second and third through vias, respectively, and stacked above an interposer. First, second, and third interface connections can be formed between the DRAM semiconductor devices. A first wiring of the interposer can be connected at a central portion of a first external connection that receives a first power supply potential. A second wiring of the interposer can be connected to a second external connection that receives a first data signal.

Abstract: A device can include a temperature circuit that can selectively set one of a plurality of temperature ranges. Each temperature range can have a temperature range upper limit value and a temperature range lower limit value. The temperature circuit can be disabled in response to a detection of a transition in a power supply voltage. In some embodiments, the temperature circuit can also be enabled a predetermined time period after the detection of the transition in the power supply voltage.

Abstract: A method can include, in response to a power supply voltage transition, setting a temperature window to a first temperature range by operation of a temperature circuit formed on a semiconductor device. In response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A method of operating a semiconductor device powered by a first power supply potential can include: generating an assist signal with an enable logic level in response to a voltage window detection circuit indicating the first power supply potential is in a first voltage window at a lower end of an operating range of the semiconductor device and generating the assist signal with a disable logic level in response to the voltage window detection circuit indicating the first power supply potential is in a second voltage window at an upper end of the operating range of the semiconductor device. Read or write operations to an SRAM can have improved reliability when the assist signal has the enable logic level.

Abstract: A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; and the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation

Abstract: A method can of operating a semiconductor device can include generating a read or write assist signal having an enable logic level in response to a power supply potential being in a first voltage window and a disable logic level in response to the power supply potential being in a second voltage window. Access operations to a static random access memory (SRAM) cell can be altered in response to the assist signal having the assist enable logic level. The second voltage window can be larger than the first voltage window.

Abstract: A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, can include: generating at least one assist signal in the normal mode of operation wherein, when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal, and inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated.

Abstract: A method of operating a semiconductor device that is powered by a first power supply potential can include detecting a change in at least one voltage window signal, the voltage window signal indicates a predetermined voltage window in which a potential of the first power supply potential is located; latching the at least one voltage window signal to provide at least one latched voltage window signal; and generating at least one assist signal in response to at least one latched voltage window signal; wherein the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal.

Abstract: A semiconductor device powered by a first power supply potential, can include a voltage detector circuit coupled to receive the first power supply potential and configured to provide at least one voltage window signal, the at least one voltage window signal indicating a predetermined voltage window in which the first power supply potential is located; an assist control circuit configured to provide at least one assist signal in response to the at least one voltage window signal; wherein the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell, as compared to the read or write operations without the at least one assist signal.

Abstract: A semiconductor device can include a voltage detector circuit configured to generate a first potential that is essentially proportional to a first power supply potential and to provide a first and second voltage window signal by comparing the first potential to a first and second reference potential. The voltage window signals indicate voltage windows in which the first power supply potential is located. An assist control circuit receives the voltage window signals and provides at least one assist signal which can alter read or write operations to a static random access memory cell.

Abstract: A package can include first and second semiconductor devices stacked in a first direction. The first semiconductor device can include a first circuit formed on the first semiconductor device that provides a first potential greater than a ground potential at a first circuit output, and a second circuit coupled to receive the first circuit output. The second semiconductor device can include a first through via providing a first electrical connection between a first side and a second side of the second semiconductor device, and a third circuit. The first circuit output can be electrically connected to the first through via at the first side of the first semiconductor device and the third circuit can be electrically connected to the first through via at the second side of the first semiconductor device to receive the first potential.

Abstract: A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

Abstract: A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient.

Abstract: A package can include a first semiconductor device and a second semiconductor device stacked in a first direction. The first semiconductor device can include a first through via providing a first electrical connection in the first direction between a first side and a second side opposite the first side of the first semiconductor device, and a first circuit that provides a first potential greater than a ground potential at a first circuit output. The first circuit output can be directly connected with wiring layers to the first via at the first side. The second semiconductor device can be electrically connected to the first through via at the second side of the first semiconductor device to receive the first potential.

Abstract: A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.