Patents by Inventor David Burnett

David Burnett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7817466
    Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 19, 2010
    Assignees: STMicroelectronics (Crolles 2) SAS, Freescale Semiconductor, Inc.
    Inventors: Richard Ferrant, Franck Genevaux, David Burnett, Gerald Gouya, Pierre Malinge
  • Publication number: 20100196835
    Abstract: A single burner snow melter is capable of a snow start. The burner assembly has a fuel burner having adjustable combustion output and a nozzle through which products of combustion emerge, and a combustion chamber which has a first portion in substantially air-tight communication with the fuel burner and which encloses the nozzle. A second portion of the combustion chamber is shaped and dimensioned such that the second portion is placed into a snow melting receptacle or pit. The combustion chamber has a plurality of directional discharge means formed at least on its second portion through which products of combustion from the fuel burner emerge, and thus agitate, and melt snow loaded into a tank or pit. The burner assembly also includes an air cooling assembly for supplying air to cool at least the first portion of the combustion chamber.
    Type: Application
    Filed: June 16, 2009
    Publication date: August 5, 2010
    Applicant: Trecan Combustion Limited
    Inventors: David Burnett, Glen Burnett, Steven Meredith
  • Patent number: 7675806
    Abstract: A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: March 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bradford Hunter, David Burnett, Troy Cooper, Prashant Kenkare, Ravindraj Ramaraju, Andrew Russell, Shayan Zhang, Michael Snyder
  • Patent number: 7609541
    Abstract: A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: October 27, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James David Burnett, Glenn C. Abeln, Jack M. Higman
  • Publication number: 20090086535
    Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.
    Type: Application
    Filed: May 30, 2008
    Publication date: April 2, 2009
    Applicant: STMicroelectronics SA
    Inventors: Richard Ferrant, Franck Genevaux, David Burnett, Gerald Gouya, Pierre Malinge
  • Patent number: 7455060
    Abstract: A startup burner assembly for use in snow melting applications, and which permits initiation of snow melting without first supplying water as a coolant. The startup burner assembly comprises a fuel burner having adjustable combustion output and a nozzle to facilitate the emergence of products of combustion, and a combustion chamber having a first portion in substantially air-tight communication with the fuel burner and enclosing the nozzle and a second portion shaped and dimensioned for disposition into a snow melting receptacle or pit. The combustion chamber has a plurality of discharge holes formed at least on the second portion thereof to permit the egress of products of combustion from the fuel burner into the tank or pit, and thereby permit agitation and melting of snow loaded therein, The startup burner assembly also includes an air cooling assembly for supplying air to cool at least the first portion of the combustion chamber.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: November 25, 2008
    Assignee: Trecan Combustion Limited
    Inventors: David Burnett, Steven Meredith, Glen Burnett
  • Patent number: 7431402
    Abstract: A rock boring device includes a rotary disc cutter. The disc cutter is driven in an oscillating manner and may be driven or free to nutate, and the device includes a mounting section for the rotary disc cutter and a driven section. The mounting section may be angularly offset from the axis of the driven section whereby the rotary disc cutter can oscillate and/or nutate.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: October 7, 2008
    Assignee: Odyssey Technology Pty Ltd
    Inventors: Anthony John Peach, Alwyn Arthur Jones, Anton Josep Jurasovic, Geoffrey Peter Johnstone, Wayne Anthony Cusick, David Burnett Sugden
  • Publication number: 20080158938
    Abstract: A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: James David Burnett, Glenn C. Abeln, Jack M. Higman
  • Publication number: 20070280026
    Abstract: A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.
    Type: Application
    Filed: May 17, 2006
    Publication date: December 6, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Bradford Hunter, David Burnett, Troy Cooper, Prashant Kenkare, Ravindraj Ramaraju, Andrew Russel, Shayan Zhang, Michael Snyder
  • Patent number: 7195983
    Abstract: A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 27, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gowrishankar L. Chindalore, James David Burnett, Craig T. Swift, Ramachandran Muralidhar
  • Patent number: 7182407
    Abstract: A rock boring device (10) including a rotary disc cutter (11). The disc cutter (11) is driven in an oscillating manner and also driven or free to nutate, and the device includes a mounting section (22) for the rotary disc cutter and a driven section (21), and wherein the mounting section (22) is angularly offset from the axis of the driven section whereby the rotary disc cutter will both oscillate and nutate.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: February 27, 2007
    Assignee: Odyssey Technology Pty Ltd
    Inventors: Anthony John Peach, Alwyn Arthur Jones, Anton Josep Jurasovic, Geoffrey Peter Johnstone, Wayne Anthony Cusick, David Burnett Sugden
  • Publication number: 20060231214
    Abstract: In a top down, bottom up blind with a fixed headrail as well as an intermediate or moving rail and bottom rail at least one spring is provided in the headrail or in the intermediate rail and is connected to the lift cords that raise and lower the intermediate rail. When the intermediate rail is fully raised to abut the headrail, the spring or springs pulls a portion of each lift cord into the headrail or intermediate rail. Consequently, the spring or springs compensate for the slippage of the lift cords that control the intermediate rail and there is no gap between the headrail and the fully raised intermediate rail.
    Type: Application
    Filed: April 14, 2005
    Publication date: October 19, 2006
    Inventors: William Whyte, James Tyner, David Burnett
  • Patent number: 7105395
    Abstract: A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: September 12, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James David Burnett, Gowrishankar L. Chindalore, Craig T. Swift, Ramachandran Muralidhar
  • Publication number: 20060137677
    Abstract: A startup burner assembly for use in snow melting applications, and which permits initiation of snow melting without first supplying water as a coolant. The startup burner assembly comprises a fuel burner having adjustable combustion output and a nozzle to facilitate the emergence of products of combustion, and a combustion chamber having a first portion in substantially air-tight communication with the fuel burner and enclosing the nozzle and a second portion shaped and dimensioned for disposition into a snow melting receptacle or pit. The combustion chamber has a plurality of discharge holes formed at least on the second portion thereof to permit the egress of products of combustion from the fuel burner into the tank or pit, and thereby permit agitation and melting of snow loaded therein, The startup burner assembly also includes an air cooling assembly for supplying air to cool at least the first portion of the combustion chamber.
    Type: Application
    Filed: June 29, 2005
    Publication date: June 29, 2006
    Inventors: David Burnett, Steven Meredith, Glen Burnett
  • Publication number: 20060057918
    Abstract: The present invention is directed to a material, or articles made from the material, which provide water resistance and thermal insulation and may be reversible.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 16, 2006
    Inventor: David Burnett
  • Patent number: 7003470
    Abstract: A system and method for tracking and reporting the flow of funds between participants in an academic health center including a school of medicine, a hospital and a faculty clinical practice. The participants identify transactions between the participants and other entities. The participants then list all of the sources of funds and uses of funds for each department within an participant. The lists are analyzed to generate departmental sources of funds and uses of funds statements. The flow of funds include normalized hidden sources of funds, such as unreimbursed expenses. The lists are used to generate standardized and customized departmental statements. Using the standardized departmental statements and participant statements, departmental and participant ratios cab be generated. The ratios allow the participants to compare the participant's departments with each other as well as with other participant's departments and with other academic health centers.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: February 21, 2006
    Assignee: University Healthsystem Consortium
    Inventors: Robert J. Baker, David A. Burnett, Michael A. Geheb
  • Publication number: 20050263013
    Abstract: A substantially flat, heat-resistant baking sheet has a baking surface, a rolled periphery and a baking area within that periphery. The baking area has numerous through-holes. A generally upright wall, integrally formed with the sheet, extends along the first part of the periphery, defining an upper edge. The height of the wall varies from a maximum to a minimum predetermined height, and the wall substantially encloses the baking area along the first part of the periphery. In the example shown, the baking sheet is rectangular: the wall extends along three sides and the fourth side has no wall. A baked product can be slid or pushed off this fourth side without being lifted, the side serving as a slide-off chute or ramp. Condensation between the baking sheet and the baked product evacuates through the holes to allow the surface against the sheet to bake to a crisper consistency.
    Type: Application
    Filed: March 16, 2005
    Publication date: December 1, 2005
    Inventors: Jeff Siegel, Adam Krent, David Burnett, William Lazaroff
  • Publication number: 20050108802
    Abstract: A generally C-shaped body for hand protection and grip enhancement includes a finger receiving pocket at a first end of the body and a thumb receiving pocket at a second end of the body. The fingers of a user are placed in the finger receiving pocket, while the thumb is placed in the thumb receiving pocket. This causes the user's palm to rest on a convex hinge portion. The finger receiving pocket and the thumb receiving pocket helps the user bend the finger receiving pocket and the thumb receiving pocket for gripping objects.
    Type: Application
    Filed: November 20, 2003
    Publication date: May 26, 2005
    Inventors: David Burnett, William Lazaroff
  • Publication number: 20050087077
    Abstract: A cookie baking sheet is formed of substantially flat heat-resistant material including a baking surface in a first plane and defining a rolled peripheral edge and a baking area within the peripheral edge. A generally upright wall is integrally formed with the sheet material and extends along only a first portion of the periphery. This wall defines an upper edge contained within a second plane that is inclined relative to and meeting the first plane substantially along a second portion of the periphery. The upright wall is provided with a variable vertical height from a maximum predetermined height to a minimum predetermined height relative to said first plane. This variable height wall substantially encloses the baking area along the first portion of the peripheral edge. In the disclosed embodiment the baking sheet is rectangular and the upright wall extends along three of the sides while the fourth side is not founded by a wall.
    Type: Application
    Filed: November 22, 2004
    Publication date: April 28, 2005
    Inventors: Jeff Siegel, Adam Krent, David Burnett, William Lazaroff
  • Patent number: 6846716
    Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: January 25, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon, James David Burnett, Rana P. Singh, Paul A. Grudowski