Abstract: The present invention provides a roasting apparatus that includes a roasting pan that reliably secures an improved roasting rack. The roasting rack is secured in retaining channels on respective handle bosses providing a 4-point support system that resists lateral and transverse shifting during use. A pair of handles extends along a long axis of the roasting rack enabling simple and secure separation of the roasting rack from the roasting pan.

Abstract: An erase of a non-volatile memory (NVM) is achieved by first using oxide tunneling followed by hot hole injection (HHI). The subsequent use of HHI completes the erase that the tunneling cannot complete due to saturation. By first using tunneling, preferably Fowler-Nordheim tunneling (FNT), the damage to a bottom dielectric that normally occurs by HHI is significantly reduced. The damage due to HHI is significantly greater at the beginning of the erase when the electric field is greater. By reducing the damage due to HHI, the bottom dielectric can be smaller than that normally used for HHI so that high voltages are not required. Accordingly, the transistors in the periphery do not need to be so oversized as is normally required for HHI and thus saving area and power.

Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Abstract: An erase of a non-volatile memory (NVM) is achieved by first using oxide tunneling followed by hot hole injection (HHI). The subsequent use of HHI completes the erase that the tunneling cannot complete due to saturation. By first using tunneling, preferably Fowler-Nordheim tunneling (FNT), the damage to a bottom dielectric that normally occurs by HHI is significantly reduced. The damage due to HHI is significantly greater at the beginning of the erase when the electric field is greater. By reducing the damage due to HHI, the bottom dielectric can be smaller than that normally used for HHI so that high voltages are not required. Accordingly, the transistors in the periphery do not need to be so oversized as is normally required for HHI and thus saving area and power.

Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Abstract: The addition of microspheres of barium titanate glass to conventional friction compositions for molding automotive and other brake elements and similar friction elements, results in substantial new and unexpected improvements with respect to the production of and processing of uniform, homogeneous molding compositions for forming the present friction elements. The formed friction pads, disks etc., have unexpectedly improved performance properties such as heat dissipation properties leading to improved, reduced wear over prolonged periods of use.

Abstract: Novel microbead coating compositions having improved binding properties for the glass microbeads suspended therein, which compositions also have superior bonding properties for substrates so as to be resistant to peeling or flaking therefrom after drying. These novel binding and bonding properties are unexpectedly produced by the addition of microparticles of ground rubber, crumb rubber or pelletized rubber, to microbead coating compositions containing a resinous binder material and, optionally, other color-enhancing particles such as pigments, glass flakes, metallic flakes, mica and similar materials.

Abstract: The addition of microspheres of barium titanate glass to conventional friction compositions for molding automotive and other brake elements and similar friction elements, results in substantial new and unexpected improvements with respect to the production of and processing of uniform, homogeneous molding compositions for forming the present friction elements. The formed friction pads, disks etc., have unexpectedly improved performance properties such as heat dissipation properties leading to improved, reduced wear over prolonged periods of use.

Abstract: A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. P-well regions of the array are spaced apart and electrically isolated by shallow trench features. The cells of each column are positioned within a respective isolated p-well region. Control gates of sequentially corresponding memory cells in columns of the array are electrically coupled by common wordlines. Bitlines electrically couple drain regions of each memory cell in the respective columns of the memory cell array. Source lines electrically couple source regions of each memory cell in the respective columns of the array. The source lines and at least one memory cell in each column of the array are electrically coupled to the p-well region corresponding to the column of the source line and cell.

Abstract: A semiconductor device having a memory array includes memory cells (101-104), a word line (42), a first bit line (68), and a second bit line (76). Within the memory array, the first and second bit lines (68 and 76) lie at different elevations above the word line (42). Local interconnects (58) are electrically connected to the first bit line (68) and some of the current carrying electrodes (48) in the memory array. The local interconnects (58) allow offset connections to be made. For floating gate memory cells (101-104) in a NOR-type memory array architecture, programming and erasing can be performed using a relatively uniform bias between the source and drain regions (46 and 48) of a memory cell (101) to be programmed without significantly disturbing data in adjacent floating gate memory cells (102-104).

Abstract: A semiconductor device (150) is formed having a first conductive member (64) overlying a field isolation region (36) that is typically less than two microns wide. Typically, the field isolation region (36) is relatively thinner compared to wider field isolation regions. The first conductive member (64) lies between the field isolation region (36) and a second conductive member (80) to shield the substrate (20). The shielding helps to increase the field threshold voltage of the field device. The invention is particularly useful in double polysilicon process flow used in forming devices operating at a potential higher than V.sub.DD. Examples of these devices include nonvolatile memories and microcontrollers having nonvolatile memory arrays.

Abstract: A static-random-access memory (SRAM) cell has been devised which contains an access transistor having a first channel region with a first surface that lies along a first crystal plane; and a trench driver transistor having a second channel region with a second surface that lies along a second crystal plane. The first and second crystal planes belong to a single family of equivalent crystal planes, for example, the {100} family of planes. Orienting the surfaces of the channel regions of the two transistors in this fashion improves the beta ratio of the driver and access transistors and thus greatly improves the cell stability. The .beta. ratio is the ratio of the transconductances of the driver and access MOSFETs, or ##EQU1## and preferably has a value of at least three. Using a trench driver transistor improves the bit cell capacitance.

Abstract: A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (16) is formed on the substrate surface and a material layer (17) doped with fluorinated boron is formed on the dielectric layer (16). A second P-type region (22), characterized by a high dopant concentration at the substrate surface and a uniform junction profile, is formed in the substrate adjacent to the first P-type region by diffusing boron atoms from the material layer (17) through the dielectric layer (16) and into the substrate (15). The second P-type region (22) has a very shallow junction depth which is closer to the substrate surface than the first P-type region.

Abstract: A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (16) is formed on the substrate surface and a material layer (17) doped with fluorinated boron is formed on the dielectric layer (16). A second P-type region (22), characterized by a high dopant concentration at the substrate surface and a uniform junction profile, is formed in the substrate adjacent to the first P-type region by diffusing boron atoms from the material layer (17) through the dielectric layer (16) and into the substrate (15). The second P-type region (22) has a very shallow junction depth which is closer to the substrate surface than the first P-type region.

Abstract: A process for the preparation of a high titre antiserum of a desired specificity includes the steps of, a first immunological reaction between a serum sample which includes a protein to which the required antiserum is specific and an antiserum sample known to include the required antiserum, injecting into an animal a first selected antigen/antibody comples from the aforesaid first reaction, withdrawal of serum from the animal, performing a second immunological reaction between the withdrawn serum and a serum sample which includes the protein to which the required antiserum is specific, and selecting a second antigen/antibody comples from the second reaction, the first and second selected complexes including the required antiserum.

Abstract: A boom gate comprises a first-class lever counterweighted at one end adjacent to which is the lever fulcrum. The fulcrum is displaceable lengthwise of the lever through a short distance sufficient to cross the center of gravity of the lever. This movement is controlled by a mechanism and the boom lifts automatically under its own weight when the center of gravity is passed. The advantage of such a system is that the effort required to raise the boom is very little and the use of high-torque equipment is unnecessary so that the boom gate can be cheaply made. Ways of displacing the fulcrum using pneumatic pressure, a handle or an electric motor are described. Also a double-sided boom gate is described.