Abstract: A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon.

Abstract: A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.

Abstract: Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Multi-Media Card/Secure Digital (MMC/SD) card. A PCM controller accesses PCM memory devices. Various routines that execute on a CPU in the PCM controller are activated in response to commands in the host-bus transactions. The PCM system increases the throughput of one or more phase-change memory devices by performing one or more of a read-ahead memory operation, a write-ahead memory write operation, a larger page memory write operation, a wider data bus memory write operation, a multi-channel concurrent multi-bank interleaving memory read or write operation, a write-cache memory write operation, and any combination thereof.

Abstract: An apparatus and methods for an optically pumped laser that has a cascade of light-emitting interband transitions are disclosed. The apparatus disclosed contains multistep interband cascade regions able to generate a plurality of photons for a pump photon absorbed from an optical pump source. The methods disclosed teach how to produce a plurality of photons for a pump photon absorbed from an optical pump source.

Abstract: A restrictive multi-level-cell (MLC) flash memory prohibits regressive page-writes. When a regressive page-write is requested, an empty block having a low wear-level count is found, and data from the regressive page-write and data from pages stored in the old block are written to the empty block in page order. The old block is erased and recycled. A two-level look-up table is stored in volatile random-access memory (RAM). A logical page address from a host is divided by a modulo divider to generate a quotient and a remainder. The quotient is a logical block address that indexes a first-level look-up table to find a mapping entry with a physical block address that selects a row in a second-level look-up table. The remainder locates a column in the row in the second-level look-up table. If any page-valid bits above the column pointed to by the remainder are set, the write is regressive.

Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Abstract: A non-rigid system and method for stabilizing displaced bony members include a flexible unit of tethering material coupled to the displaced bony members so as to restore a desired shape, curvature of or relationship between the bony members without excessively limiting mobility of bony members located adjacent to the displaced members the rest of the portions of the motion bony segment during a restoration process.

Abstract: A concentrator for detecting biological and/or chemical materials in an environment. The concentrator comprises an engineered superlattice structure having alternating layers of elemental, binary or ternary group III-group V, or group IV-group IV semiconducting materials. A method for detecting biological and/or chemical materials in an environment using the concentrator. The method comprising exposing the concentrator to the biological and/or chemical materials in an environment and activating the superlattice structure optically or electrically followed by the detection of the biological and/or chemical materials.

Abstract: Articles of manufacture are produced from a composition comprising agave plant residue and a thermosetting polymer resin.

Abstract: Coffee bean residue is a primary constituent of new thermosetting polymer compositions and articles of manufacture. The articles are made by compression molding and curing of one or more thermosetting polymer resins blended with coffee bean residue. Other additives and fillers may also be included in the compositions.

Abstract: A fuel cell system that employs a diode electrically coupled between bipolar plates in a fuel cell of a fuel cell stack for preventing the fuel cell between the plates from reversing its polarity. The diode is a thin-sheet p-n diode including doped semiconductor layers and has a thickness relative to the thickness of the MEA in the fuel cell so that the overall stack thickness does not increase. When the fuel cell is operating properly the diode does not conduct and all of the current through the fuel cell goes through the MEA. If the electric load on the stack increases to a level beyond the capability of the fuel cell, where the potential across the fuel cell goes significantly below zero, the diode will begin to conduct so that any current that cannot travel through the MEA with the cell voltage less than one negative forward diode voltage drop is able to go around the MEA through the diode.

Abstract: A plurality of differently configured bone spinal implants for insertion in a spine have a cylindrical bore for receiving an insertion head stud. A plurality of instruments are disclosed each of which have a first connection element which is either a male or female member such as e.g., a ball and socket, a cylinder and socket and so on for forming either a stationary or articulating interchangeable joint for a plurality of disc processing heads or implant insertion heads. The plurality of disc space processing heads or implant insertion heads have a complementary second joint member for interchangeable attachment to the first connection element. The implant insertion heads or disc processing heads have different configurations for different shaped implants.

Abstract: A chisel with U.V-shaped, saw tooth or other shaped opposing blades is used to form channels in adjacent vertebrae. The chisel has a projection extending from at least one of the top and bottom surfaces to limit depth of penetration into the vertebrae. A guide member may be attached to the forward tip of the chisel to guide the chisel into the disc space to uniformly chisel both adjacent vertebrae simultaneously to form a channel in the vertebrae. The so formed channels serve as sa guide for a second chisel having no guide member. The second chisel, which may be a box chisel, is used to complete the channels to the desired depth to receive an associated implant, typically of cortical bone. Other embodiments are disclosed in which a two step box chisel has a retractable guide member for initially guiding the chisel as it forms partial channels in the vertebrae disc space. The guide member is then retracted and the channels formed to the desired depth.

Abstract: A bone fastener for stabilizing bone fragments includes a single or multiple components coupleable with one another and displaceable to a locked position of the bone fastener.

Abstract: Intervertebral implant system for intervertebral implantation, are disclosed. An intervertebral implant system according to the present disclosure includes a frame having a peripheral wall defining a space therein, and a settable material introducible into the space of the frame. The settable material is a biocompatible load bearing material including and not limited to bone, composites, polymers of bone growth material, collagen, and insoluble collagen derivatives. The settable material is injectable into the space defined by the frame. The settable material may have an initial fluid condition wherein the fluid settable material cures to a hardened condition.

Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Abstract: A memory system. The system includes at least two ferroelectric memory devices arranged sequentially. Each memory device has a data in signal and a data out signal, and the data out signal each memory device is transmitted as the data in signal of the next device in sequence. A system controller generates an initial data in signal for the first memory device. A data bus transfers data between each memory device and the system controller and an address bus provide addressing of the memory devices.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a self-timing module to adjust timing of the integrator sensing based upon a predefined voltage level.

Abstract: A method of sealing lenses includes the steps of grinding the edges of at least two lenses, cleansing the lenses, positioning the lenses next to one another, applying an adhesive to the ground edges of the lenses and placing the lenses in an oven to cure the adhesive to produce a laminated, hermetically-sealed, lens.

Abstract: A ferroelectric memory device comprises a plurality of subarrays having a plurality of bitlines and a plurality of wordlines crossing over the bitlines. Ferroelectric material is disposed between the wordlines and the bitlines to define a ferroelectric cell at each crossing of the wordlines and bitlines. Each subarray further comprises left and right voltage converters disposed on opposite sides thereof, to drive respective first and second sets of wordlines within the subarray. A plurality of global wordlines are couple to the left and right voltage converters of each subarray and are configured to establish the drive levels for respective wordlines of the subarrays. A bitline multiplexer selectively couples the bitlines of a select subarray to a plurality of sense amplifiers.