Abstract: In some embodiments, clock strobed data over one waveguide or fiber is presented. In this regard, a transfer agent is introduced to convert one or more lanes of data and a corresponding clock strobe from electrical signals to optical signals of differing wavelengths. Other embodiments are also disclosed and claimed.

Abstract: A method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link. In one embodiment, the method includes the selection of a compliance speed for a point-to-point link from at least two link frequencies supported by the point-to-point link. Once the compliance speed is selected for the point-to-point link, the point-to-point link is caused to enter a compliance testing mode. During compliance testing mode, a controller of the point-to-point link sets a compliance speed of the point-to-point link to the selected compliance speed. Once a compliance speed is set, a transmitter of the point-to-point link transmits a compliance pattern at the selected compliance speed. In one embodiment, the transmission of the compliance pattern at the selected compliance speed is used to generate a worst case eye diagram to determine compliance of the point-to-point link to a link specification. Other embodiments are described and claimed.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides detecting by a network controller a flush occurring on a host bus of a DM (“direct messaging”) packet to a memory from a first cache line associated with a first processor; obtaining and storing the DM packet at a second cache line associated with the network controller; and sending the DM packet over a network to a third cache line associated with a second processor.

Abstract: A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.

Abstract: A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface.

Abstract: CMOS optical receiver and optical transmitters are described. The optical receiver is formed from a CMOS CCD which is modified to immediately output all information indicative of incoming light, i.e., with no transfer gate. The optical transmitter is formed of a modulation window device. Both the optical transmitter and optical receiver are located on-chip with a microprocessor and form the I/O for the microprocessor. Since the modified I/O is serial, a serial to parallel converter, and parallel to serial converter are provided.

Abstract: Embodiments of the invention provide a state machine for initializing the physical layer of a point-to-point link-based interconnection. Embodiments of the invention use explicit handshakes between the interconnected agent to advance states and provide a variety of optional features for flexibility and efficiency.

Abstract: Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

Abstract: A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

Abstract: A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback test based on detection of a header within a packet. The slave and master agent to support exit out of the loopback test based on whether the loop count is finite.

Abstract: A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register.

Abstract: A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output (“I/O”) unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

Abstract: A method and apparatus for retraining skew compensation in an interface is presented. In one embodiment, a retraining interval is determined, and counters in the transmitting agent and receiving agent count up until the retraining interval is reached. A tracking unit used to select one of several interpolated clocks may then be powered up, and a special retraining phit may be sent across the interface. During the retraining process, the transfer of flits into and out of the flow-control mechanism may be inhibited. When the retraining process is finished, the tracking unit may be powered down.

Abstract: Methods and apparatuses for determining clock failure for a multi-agent system employing a link-based interconnection scheme using a forwarded clock. For one embodiment of the invention, the cessation of the forwarded clock initiates a clock failure determination process. For one embodiment of the invention, upon a determination of clock failure, an alternate clock lane is implemented using a pre-designated data lane.

Abstract: A method and apparatus for advancing initialization messages when initializing an interface is presented. In one embodiment, one of a sequence of training sequence messages are sent in serial mode across the data lanes of a generally-parallel interface between two agents. When one agent correctly receives a fixed number of messages, it may begin sending its messages with an acknowledgement. Thereafter, when that agent correctly receives a fixed number of messages including an acknowledgement, that agent may advance to sending the next training sequence messages in the sequence.

Abstract: A method and apparatus for advancing initialization messages in a lock-step manner when initializing an interface is presented. In one embodiment, a lane receiver may transition to a receiver ready attribute when a given number of current training sequence messages is correctly received. When the receiver ready attributes of all the lanes are set, a local acknowledgement attribute may be set. Similarly, a lane receiver may transition to a remote acknowledgement attribute when a given number of current training sequence messages with acknowledgement field set is correctly received. When both the local acknowledgement attribute and the remote acknowledgement attribute are set, the port may advance to the next training sequence messages.

Abstract: A technique to perform virtualization of lanes within a common system interface (CSI) link. More particularly, embodiments described herein relate to virtualizing interconnective paths between two or more electronic devices residing in an electronic network.

Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

Abstract: A technique is described by which two link agents with ports coupled together using a point-to-point interconnect in a system exchange their link width support capabilities and negotiate a link width that is mutually agreeable. The interconnect between each pair of agents comprises a pair of uni-directional links having multiple electrical wires, or lanes, where one link is used by a first agent to transmit data to a second agent and another link is used by the second agent to transmit data to the first agent.

Abstract: Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.