Patents by Inventor David Eggleston
David Eggleston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100064089Abstract: There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device.Type: ApplicationFiled: November 16, 2009Publication date: March 11, 2010Applicant: Micron Technology, Inc.Inventor: David Eggleston
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Patent number: 7624211Abstract: There is provided a method and apparatus for bus width negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device.Type: GrantFiled: June 27, 2007Date of Patent: November 24, 2009Assignee: Micron Technology, Inc.Inventor: David Eggleston
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Publication number: 20090225606Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: ApplicationFiled: May 21, 2009Publication date: September 10, 2009Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20090204871Abstract: Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.Type: ApplicationFiled: April 17, 2009Publication date: August 13, 2009Inventors: David Eggleston, Bill Radke
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Patent number: 7548824Abstract: A system and method for an automated analysis system for semiconductor manufacturing fabrication is disclosed. The system includes one or more site databases that each store data generated by an associated one or more semiconductor fabrication plants, a configuration database, and a server communicatively coupled to the one or more site databases and the configuration database, the server to analyze the data from the one or more site databases upon a request by a client, the data to be analyzed based on configuration settings in the configuration database that provide uniform configuration synchronization for applying algorithms to the data.Type: GrantFiled: June 27, 2006Date of Patent: June 16, 2009Assignee: Intel CorporationInventors: Sutirtha Bhattacharya, Brenda Buttrick, David Eggleston, Ayman Fayed, Raj Mohan, Girish Nirgude, Sanjay Patel, Ashit Sawhney, Raghu Yeluri
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Patent number: 7545682Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: July 19, 2006Date of Patent: June 9, 2009Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Patent number: 7523381Abstract: Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.Type: GrantFiled: September 1, 2005Date of Patent: April 21, 2009Assignee: Micron Technology, Inc.Inventors: David Eggleston, Bill Radke
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Patent number: 7480762Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: May 2, 2005Date of Patent: January 20, 2009Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20090013148Abstract: Apparatus and methods provide associative mapping of the blocks of two or more memory arrays such that data, such as pages of data, from the good blocks of the two or more memory arrays can be read in an alternating manner for speed or can be read in parallel for providing data to relatively wide data channels. This obviates the need for processor intervention to access data and can increase the throughput of data by providing, where configured, the ability to alternate reading of data from two or more arrays. For example, while one array is loading data to a cache, the memory device can be providing data that has already been loaded to the cache.Type: ApplicationFiled: July 3, 2007Publication date: January 8, 2009Applicant: MICRON TECHNOLOGY, INC.Inventor: David Eggleston
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Publication number: 20090006691Abstract: There is provided a method and apparatus for bus arbitration. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device.Type: ApplicationFiled: June 27, 2007Publication date: January 1, 2009Inventor: David Eggleston
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Publication number: 20070299634Abstract: In one embodiment, a system and method for an automated analysis system for semiconductor manufacturing fabrication is disclosed. In one embodiment, the system comprises one or more site databases that each store data generated by an associated one or more semiconductor fabrication plants, a configuration database, and a server communicatively coupled to the one or more site databases and the configuration database, the server to analyze the data from the one or more site databases upon a request by a client, the data to be analyzed based on configuration settings in the configuration database that provide uniform configuration synchronization for applying algorithms to the data. Other embodiments are also described.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventors: Sutirtha Bhattacharya, Brenda Buttrick, David Eggleston, Ayman Fayed, Raj Mohan, Girish Nirgude, Sanjay Patel, Ashit Sawhney, Raghu Yeluri
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Publication number: 20070294522Abstract: A synchronous Flash memory device is described that enhances initialization and boot memory device identification in synchronous memory systems. A boot memory is typically a separate device that is tied to a specific chip select line and/or address range of a system, whereas synchronous Flash memory generally can be placed in any available memory slot and assigned one of several possible chip selects and address ranges. This lack of predictability makes installing a boot memory based on a non-volatile synchronous memory device difficult. A synchronous Flash boot memory device of the detailed invention is adapted to identify itself and its chip select/address range to the memory controller at power up, reset, or upon receiving an identification request. This allows the utilization of the detailed synchronous Flash memory as a boot memory in synchronous systems where a reserved boot memory slot and/or chip select are not provided.Type: ApplicationFiled: August 23, 2007Publication date: December 20, 2007Inventors: Cliff Zitlaw, Frankie Roohparvar, David Eggleston
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Patent number: 7272709Abstract: A synchronous Flash memory device is described that enhances initialization and boot memory device identification in synchronous memory systems. A boot memory is typically a separate device that is tied to a specific chip select line and/or address range of a system, whereas synchronous Flash memory generally can be placed in any available memory slot and assigned one of several possible chip selects and address ranges. This lack of predictability makes installing a boot memory based on a non-volatile synchronous memory device difficult. A synchronous Flash boot memory device of the detailed invention is adapted to identify itself and its chip select/address range to the memory controller at power up, reset, or upon receiving an identification request. This allows the utilization of the detailed synchronous Flash memory as a boot memory in synchronous systems where a reserved boot memory slot and/or chip select are not provided.Type: GrantFiled: December 26, 2002Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventors: Cliff Zitlaw, Frankie F. Roohparvar, David Eggleston
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Patent number: 7193899Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: December 3, 2004Date of Patent: March 20, 2007Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20070061672Abstract: Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.Type: ApplicationFiled: September 1, 2005Publication date: March 15, 2007Inventors: David Eggleston, Bill Radke
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Publication number: 20060256624Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: ApplicationFiled: July 19, 2006Publication date: November 16, 2006Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20050204091Abstract: A high density non-volatile memory system, card, and device is described that incorporates a synchronous interface. This is accomplished through use of an external or embedded controller and/or memory buffer to manage the high density non-volatile memory device(s) to present it as a conventional memory device having a synchronous interface that is accessible by row and column address. This allows the high density non-volatile memory to support in-place code execution and allows it to be booted from. Additionally, this incorporation eliminates the overhead of drivers and/or operating system support required to utilize and present conventional high density non-volatile memory devices and moves it internal to the memory device. This simplifies the use and design effort in the overhead and specialized interfacing of high density non-volatile memories and in particular, NAND architecture Flash memories, while reducing the production cost through use of less expensive high density non-volatile memory.Type: ApplicationFiled: March 11, 2004Publication date: September 15, 2005Inventors: Kevin Kilbuck, David Eggleston
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Publication number: 20050190599Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: ApplicationFiled: May 2, 2005Publication date: September 1, 2005Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Patent number: 6906961Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: GrantFiled: June 24, 2003Date of Patent: June 14, 2005Assignee: Micron Technology, Inc.Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
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Publication number: 20050099845Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.Type: ApplicationFiled: December 3, 2004Publication date: May 12, 2005Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays