Abstract: A communication system includes a plurality of requestors and a plurality of responders representing resources. A protocol exercised by all elements provides accurate and consistent interconnection of all elements in a system where messages may be delayed or lost. Requestors are provided with means to transmit a request for use of a plurality of resources, respond to acceptances from one or more responders and create a cooperative relationship by transmitting a confirmation to one responder and cancellation of the request to all other responders. Responders become committed to a requestor by signalling an acceptance to a request if a previous acceptance has not been transmitted, or if the resource is not already committed to another requestor, and a subsequent confirmation signal is received. The responder does not become committed after transmitting an acceptance if the next signal directed to it from the requestor is a request cancellation.

Abstract: A system is described for enabling the connection of a diagnostic/debugging processor to another host processor for the purpose of troubleshooting that processor's hardware and software. The system is composed of an interface between the diagnostic/debugging processor per se and the host processor to be diagnosed, and of software resident in the diagnostic processor to perform functions required by the user of the system. The system is specifically designed for use with a host processor utilizing LSSD design rules.

Abstract: The technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system. The width of the address field is greater than the number of lines on the bus. For example, addresses are three bytes wide, and the bus is one byte wide, thereby reducing the number of pins required on the processor and the subsystems. For communication between the processor and a given memory subsystem, only those bytes of a selected address which differ from the corresponding bytes of a previous address are transmitted sequentially for accessing a selected memory location.