Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Abstract: Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Abstract: Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Imaging arrays are electronic devices that sense light and output electrical signals representative of the sensed light. An imaging array comprises thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns defective or malfunctioning photodetectors. Defective photodetectors typically result in erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for defective photodetectors. One exemplary embodiment includes one or more photodetectors that are substantially smaller than conventional photodetectors, for example about 10 or 25 square microns.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).

Abstract: A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).