Abstract: An improved method of making a semiconductor device such as an N-channel, double level poly, MOS read only memory or ROM array is provided; the array is of very dense structure and may be electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon or metal row address lines. The electrical programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate. The very dense array results from a simplified manufacturing process generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride (functioning as an oxidation mask) are created in one mask step before field oxide is grown, then a perpendicular pattern of conductive strips is etched using a second mask step.

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.

Abstract: An MOS read only memory or ROM formed by the standard N-channel silicon gate manufacturing process uses a cell structure which allows implant programming after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon strips and output and ground lines are metal strips perpendicular to the address lines; these metal strips make contact to the sources and drains defined by N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by selective ion implant through the polysilicon gates and thin gate oxide, using photoresist as a mask, after application of the metal level. The ion implant is not required to penetrate through the metal lines.

Abstract: A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh circuitry which automatically produces a refresh operation invisible to the CPU. The refresh circuitry includes an address counter and a multiplexer to insert the refresh address when an internal clock indicates a refresh cycle. The refresh address counter is incremented after each refresh cycle. If a refresh command is being executed when an address presented, the refresh operation is completed then the device is accessed in the usual manner. By specifying the access time of the device as the sum of the usual access type plus the time needed for refresh, the internal refresh is invisible to the CPU.

Abstract: A contact programmable, small cell area MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines are metal, gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", by presence or absence of a contact engaging the polysilicon gate over the thin gate oxide.

Abstract: A memory system for a digital processor device having a 16-bit bidirectional bus with multiplexed addresses and data employs separate memory devices for the high order and low order data bytes. When less than 64 K words of memory are used, there are unused address lines in the bus. A microcomputer may use memory devices partitioned 4 K.times.8, needing 12 address pins. Both devices are constructed the same, but one accesses the low order byte and the other the high order byte under control of a single byte-select terminal. Mapping of the bus to memory device connections and internal connection of unused pins to address inputs or data input/output lines within the memory devices, along with the byte-select function, allow a single type of device to function in either position.

Abstract: A floating gate type electrically programmable memory device is made by an N-channel double-level polysilicon self-aligned process which results in a very dense array. The programming inefficiency caused by inherent resistance of elongated diffused regions used as column lines is overcome by a capacitive discharge programming method. Distributed capacitance of the column lines is charged to the programming voltage before the selected row line is brought to a high voltage, producing a pulse of current through the cell. A series of these programming pulses may be used.

Abstract: An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "O's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

Abstract: A contact programmable, small cell area MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines are metal, gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", by presence or absence of a contact engaging the polysilicon gate over the thin gate oxide.

Abstract: A semiconductive device and a method for producing the semiconductive device, wherein random defects or inaccuracies in precise registrations of certain patterns are compensated by the introduction of selected impurities. The selected impurities bring about changes in the electrical characteristics of those portions of the semiconductor affected by the random defects or registration inaccuracies so as to prevent them from causing malfunctions in the completed devices.

Abstract: An improved arrangement for providing cathode heating current in a visual display wherein pulses of heating current are sequentially applied at brief intervals, the magnitude of the current and the intervals being coordinated with the cathode thermal inertia so as to maintain cathode temperature within an operative range during the off periods, and wherein potentials for activating the display are applied during such off periods.

Abstract: A semiconductor integrated circuit is shown in the form of an MOS read only memory or ROM formed by standard N-channel silicon gate manufacturing methods. Address lines and gates are polysilicon strips, output lines are metal strips, and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", by the presence or absence of a contact between an output metal line and an N+ drain region of a transistor, or by the presence or absence of a moat forming the transistor of the cell. In moat programming, if both cells in a pair are programmed as zeros, then both contact and moat are eliminated, thus reducing capacitive loading and increasing speed. In contact programming, the moat can be removed for inactive bits to reduce loading.

Abstract: A semiconductor memory circuit includes two cross coupled driver transistors with storage nodes connected to data lines by coupling transistors, providing a static RAM cell. Load resistors are connected from the storage nodes to the data lines rather than to a voltage supply, and the data lines are maintained at an intermediate voltage level in standby operation. The intermediate voltage is sufficient to hold the driver transistors in a stable state, one conducting and one off.

Abstract: A cell for a semiconductor memory of the static type employs two conventional MOS transistors along with a field implanted resistance which functions as a grounded-gate junction FET. Along with other resistor elements, these devices provide a grounded-gate amplifier with voltage gain and a source follower, creating a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.

Abstract: An N-channel double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate. A very dense array is obtained by a simplified manufacturing process which is generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride oxidation mask are applied, field oxide is grown, then a perpendicular pattern of strips is etched, removing field oxide as well as parts of the original strips, providing a diffusion mask. The second level poly is then applied as strips overlying the original strips.

Abstract: A digital processor which may be used in a calculator is provided by an MOS/LSI semiconductive chip which contains a bit-parallel arithmetic unit for operating on data stored in a random access memory. Selector units determine which of several sources produce the inputs to the arithmetic unit. The random access memory has X and Y, or page and word addressing. Part of the random access memory provides direct access for readout. Numerical data at the Y address in the direct access memory is always available at the selector units for input to the arithmetic unit, at the same time that data at the same Y address but another X address is read out to be also an input to the arithmetic unit. The direct access part of the memory is addressed for write in by the same addressing means as the remainder of the memory. This arrangement reduces the number of machine cycles needed for arithmetic operations, and so provides faster calculations.

Abstract: An N-channel, double level polysilicon, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate. A very dense array is obtained by a simplified manufacturing process which is generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride oxidation mask are applied, field oxide is grown, then a perpendicular pattern of strips is etched, removing field oxide as well as parts of the original strips, providing a diffusion mask. The second level polysilicon is then applied as strips overlying the original strips.

Abstract: An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "0's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

Abstract: A cell for a semiconductor memory of the static type employs only one conventional MOS transistor, along with a field implanted resistance and a vertical P-channel junction-type field effect transistor. These elements, along with a resistor element which may be another field implanted resistance or a polysilicon implanted resistance, provide a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.

Abstract: An integrated semiconductor memory device of the static type uses a memory cell circuit having an MOS transistor of the conventional type as the access transistor, along with a resistance element buried under field oxide and an inverted field-effect transistor formed by a polycrystalline layer over a gate region. The MOS transistor connects a storage node to the access line, and the inverted field-effect transistor connects the storage node to reference potential. The storage node is connected to a second node through the resistance element, and a resistor connects the second node to a voltage supply; the magnitude of the resistance element varies according to the voltage on the storage node. The impedance of the inverted field-effect is determined by the voltage on the second node which is a moat region forming the gate.