Abstract: An apparatus for testing sensors in a media includes a chamber portion (240) for holding the sensors, tanks (320, 340) for supplying the media to the chamber portion (240) and coupled in parallel to the chamber portion (240), a pressure generator (310) coupled to the tanks (320, 340), and a heat exchanger (323, 324) adjacent to the tanks (320, 340). The media is simultaneously heated to different temperatures and pressurized to different pressures in the tanks (320, 340). Then, the media is delivered from the tanks (320, 340) to the chamber portion (240), and the sensors detect the media at the different temperatures and pressures.

Abstract: A non-zero temperature coefficient of offset (Tco) in a semiconductor device (5) is adjusted by reducing the amount of adhesive material used to secure a first structure to a second structure. An adhesive layer (14) used to secure a sensor die (11) to a constraint die (12) in a pressure sensor application is reduced in thickness and/or formed so that adhesive material does not completely cover the constraint die (12). The Tco is further adjusted by reducing the amount and/or patterning the adhesive layer (18) used to secure the sensor (10) to its package (16).

Abstract: A media compatible microsensor structure (11) for sensing an environmental condition in a harsh media includes an inorganic protective film (17) covering portions of the structure that will be exposed to the harsh media. In one embodiment, the microsensor structure (11) includes a microsensor package (12), a microsensor device (16) bonded to the microsensor package (12), a leadframe (13), a connective wire (14) connecting the microsensor device (16) to the leadframe (13), and an inorganic protective film (17) formed on all or portion of the exposed surfaces of the structure.

Abstract: A pressure sensor (32) having a transducer (34) disposed on a top surface of an active die (38). The transducer has a doped region (42), the active die is disposed on a mounting substrate (70), and an interconnect opening (48) is disposed at an edge (90) of the active die. A metal layer (50) is disposed in the interconnect opening and on the top surface of the active die to be in electrical contact with the doped region. A conductive bump (76) is disposed on the mounting substrate in electrical contact with the metal layer and a conductive trace (74) on the mounting substrate.

Abstract: An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

Abstract: A vertically integrated sensor structure (60) includes a base substrate (71) and a cap substrate (72) bonded to the base substrate (71). The base substrate (71) includes a transducer (78) for sensing an environmental condition. The cap substrate (72) includes electronic devices (92) formed on one surface to process output signals from the transducer (78). The sensor structure (60) provides an integrated structure that isolates sensitive components from harsh environments.

Abstract: A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

Abstract: To eliminate undesirable energy recorded during seismic surveying, a trace that models the undesirable energy on the recorded data trace is prepared. The model trace is first estimated using a suitable technique, such as wavefield extrapolation. Then, the model trace is modified using a best estimate of the amplitude, phase and time delay differences between the model trace and the data trace. The estimated amplitude, phase and time delay differences may be used to design a cross-equalization filter, which is used to cross-equalize the model trace with the data trace. Alternatively, the best estimate determination may include using a weighted sum of the model trace, its imaginary component, and their derivatives. When weighted and summed together, these components form a cross-equalized model trace that closely approximates the undesirable energy on the recorded data trace. Lastly, the cross-equalized model trace is subtracted from the data trace to substantially eliminate the undesirable energy.

Abstract: A transistor (10) is formed by utilizing an isolated well (18) within a thin epitaxial layer (14). A base mask (22) that has a base opening (23) is applied to expose a portion of the isolated well (18). A low resistance collector enhancement (24) is formed within the well (18) by doping a portion of the well (18) through the base opening (23). A base region (26) is formed overlying the collector enhancement (24) by doping the well (18) through the base opening (23). Forming the collector enhancement (24) through the base opening (23), facilitates providing the collector enhancement (24) with a small area thereby minimizing the transistor's (10) parasitic collector capacitance value, collector resistance, and transit time.

Abstract: A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

Abstract: The present invention provides method of interpolating spatially aliased seismic data. This method produces high resolution interpolated data based on a locally planar model of reflection events using a two dimensional power diversity slant stack process that transforms the data from the t-x-y domain to t-xslope-yslope domain. The present invention further provides an improved technique for the 3D interpolation of aliased events and is applicable to the interpolation of 2D seismic data.

Abstract: A method for attenuating coherent and incoherent noise in seismic signal data is provided. Seismic signal data is transformed from a time-space domain using a Radon-transform domain. In the Radon-transform domain, coherent noise is attenuated by muting and incoherent noise is attenuated by diversity stacking. Data remaining in the Radon-transform domain in transformed back to the time-space domain by an inverse Radon transform.