Abstract: An information handling system is provided which comprises: a metal enclosure; at least one circuit assembly positioned within said metal enclosure, said circuit assembly including a circuitized substrate having at least one dielectric interior layer including a first surface and at least one hole therein; means for providing electrical power to said circuitized substrate within said metal enclosure; a filler material, wherein said filler material substantially fills said at least one hole within said at least one dielectric interior layer; a first wiring layer positioned on said first surface of said at least one dielectric interior layer, wherein said first wiring layer substantially covers said at least one hole having said filler material therein, said first wiring layer assisting in retaining said filler material within said at least one hole in said at least one dielectric interior layer; a first dielectric photoresist layer positioned on said first wiring layer and on said first surface of said at lea

Abstract: A process for manufacturing circuit boards comprising providing a circuitized substrate having a dielectric surface, providing a peel apart structure including a metal layer and a peelable film, laminating the peel apart structure to the circuitized substrate with the metal layer positioned adjacent said dielectric surface, forming holes in the circuitized substrate through the peel apart structure, applying a filler material including an organic base to the peel apart structure, applying a sacrificial film onto the filler material, and applying sufficient heat and pressure to the sacrificial film to force the filler material into the holes to substantially fill the holes is provided.

Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is deposited onto a sacrificial carrier and the filler material is heated to at least partially cure it. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler the holes are filled sufficient for electrical connection through the holes. The peelable layer, sacrificial carrier and filler material remaining therebetween are peeled off the copper foil. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer.

Abstract: A circuit assembly that includes a circuitized substrate having a dielectric interior layer with a first surface and at least one hole therein. A filler material substantially fills the hole within the dielectric interior layer. A first wiring layer is positioned on the first surface of the dielectric interior layer, wherein the first wiring layer substantially covers the hole and assists in retaining the filler material within the hole in the dielectric interior layer. A first dielectric photoresist layer is positioned on the first wiring layer and on the first surface of the dielectric interior layer. The first dielectric photoresist layer also includes at least one hole therein. The filler material also substantially fills the hole within the first dielectric photoresist layer. A second wiring layer is positioned on the first dielectric photoresist layer and includes a plurality of conductive pads as part thereof.

Abstract: A novel process for circuitizing a dielectric layer, particularly for adding wiring planes, which is employed in the fabrication of circuitized structures, that does not requiring drilling of vias, yet provides good adhesion of circuitization to dielectric layer. In its broadest sense the method comprises the following steps: a. providing: a substrate; a hydrophobic, uncured, photoimagable, dielectric film having a solvent content of from about 5 to 30%; metal foil; b. contacting the metal foil and the dielectric film so that a replicate image is formed in the dielectric film; c. disposing the dielectric film on the substrate either after step a or step b; d. etching the metal foil from the dielectric film after step c; e. after step d, photoimaging the dielectric film to form vias or through holes in the dielectric film; and then metallizing the film after step e, to provide circuitization atop the dielectric film. The invention also relates to the circuitized structures produce by the method.

Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil to the substrate, and forming holes in the substrate through the foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is deposited into the holes and is heated to at least partially cure it. The surface of the filler material is seeded and electrolessly plated to form a conductive coating on the metal foil and the filler material. The coating is then patterned to form a wiring layer. A second set of holes may be formed in the circuitized substrate after the hole filling step, which are also electrolessly plated.

Abstract: A novel process for circuitizing a dielectric layer, particularly for adding wiring planes, which is employed in the fabrication of circuitized structures, that does not requiring drilling of vias, yet provides good adhesion of circuitization to dielectric layer. In its broadest sense the method comprises the following steps: a. providing: a substrate; a hydrophobic, uncured, photoimagable, dielectric film having a solvent content of from about 5 to 30%; metal foil; b. contacting the metal foil and the dielectric film so that a replicate image is formed in the dielectric film; c. disposing the dielectric film on the substrate either after step a or step b; d. etching the metal foil from the dielectric film after step c; e. after step d, photoimaging the dielectric film to form vias or through holes in the dielectric film; and then metallizing the film after step e, to provide circuitization atop the dielectric film. The invention also relates to the circuitized structures produce by the method.

Abstract: Photoimageable dielectric materials are coated on substrates, selectively exposed and developed, whereby small vias and interconnection openings are formed between adjacently spaced circuit layers. A conductive paste may be used to provide sequential layer interconnection and surface planarization. No adhesives are required in the manufacture of a circuit assembly having multiple circuit and dielectric layers, and the manufacturing method avoids the requirement for drilled through holes and blind vias.

Abstract: A semiconductor package and method for preparing same to obtain improved die adhesion to organic chip carriers has been developed. A copper die bond pad is coated with a passivation material and attached to an organic card with the same passivation material. A semiconductor die may be adhered to the coated die bond pad with either the same passivation material or a common die bond adhesive. Alternatively, the passivation material is coated only on the portion of the die bond pad where the die is attached, and common die bond adhesive attaches the die bond pad to the organic card.

Abstract: A modular structure for providing electrical interconnections achieves greatly increased wiring density by forming vias and wiring patterns by chemical (e.g. lithographic) processes rather than by mechanical processes such as punching of vias and screening patterns of conductive paste. A basic module is a power core comprising an apertured metallic foil with an insulator applied to surfaces thereof, extending through at least one aperture and exposing the metallic foil in at least one aperture. The foil in the power core provides stiffness to facilitate subsequent handling and electrical shielding between conductive layers as well as a potential power connection. Via connections of increased conductivity and robustness are formed by plating the interior of vias after lamination of a desired combination of power cores and signal cores.

Abstract: A metal carrier has a dielectric material with a thickness of less than 0.004 inch and electrical voltage insulation characteristics of at least 2500 volts formed on a surface. A donut configured land defines at least one via or opening for removing dielectric material selectively. Reflow solder is used to form electrical interconnections, and the vias provide thermal dissipation sufficient to conform to safety requirements.

Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler the holes are filled sufficient for electrical connection through the holes. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer. A permanent dielectric photoresist layer is formed over the wiring layer and via holes are formed through the photoimageable dielectric over pads and conductors of the wiring layer.

Abstract: An improved photoimagable cationically polymerizable epoxy based coating material is provided, that is suitable for use on a variety of substrates including epoxy-glass laminate boards cured with dicyandiamide. The material includes an epoxy resin system consisting essentially of between about 10% and about 80% by weight of a polyol resin which is a condensation product of epichlorohydrin and bisphenol A having a molecular weight of between about 40,000 and 130,000; and between about 35% and 72% by weight of an epoxidized glycidyl ether of a brominated bisphenol A having a softening point of between about 60.degree. C. and about 110.degree. C. and a molecular weight of between about 600 and 2,500. Optionally, a third resin may be added to the resin system. To this resin system is added about 0.

Abstract: A metal carrier has a dielectric material with a thickness of less than 0.004 inch and electrical voltage insulation characteristics of at least 2500 volts formed on a surface. A donut configured land defines at least one via or opening for removing dielectric material selectively. Reflow solder is used to form electrical interconnections, and the vias provide thermal dissipation sufficient to conform to safety requirements.

Abstract: Photoimageable dielectric materials are coated on substrates, selectively exposed and developed, whereby small vias and interconnection openings are formed between adjacently spaced circuit layers. A conductive paste may be used to provide sequential layer interconnection and surface planarization. No adhesives are required in the manufacture of a circuit assembly having multiple circuit and dielectric layers, and the manufacturing method avoids the requirement for drilled through holes and blind vias.

Abstract: The present invention relates to an arrangement in a time division multiplex link having at least two pairs of multiplexors and demultiplexors interconnected by separate transmission lines, i.e., redundant transmission systems, with delay, in which time division multiplex channels are formed through the cyclic scanning of the multiplexor inlets and demultiplexor outlets, respectively so that data signals presented to the multiplexor inlets are transferred via the time division multiplex channels in the form of sampling signals to regeneration arrangements connected to the demultiplexor outlets. The sampling signals passed over the separated (redundant) time division multiplex channels are interlaced, i.e., different delays on different transmission lines, thereby producing a resultant sampling density which, when a fault occurs, is reduced by a factor corresponding to the share of the faulty channel in the total number of channels.