Patents by Inventor David L. Harmon

David L. Harmon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5412246
    Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG..
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: May 2, 1995
    Assignee: International Business Machines Corporation
    Inventors: David M. Dobuzinsky, David L. Harmon, Srinandan R. Kasi, Donald M. Kenney, Son V. Nguyen, Tue Nguyen, Pai-Hung Pan
  • Patent number: 5330935
    Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100.ANG..
    Type: Grant
    Filed: July 21, 1992
    Date of Patent: July 19, 1994
    Assignee: International Business Machines Corporation
    Inventors: David M. Dobuzinsky, David L. Harmon, Srinandan R Kasi, Donald M. Kenney, Son Van Nguyen, Tue Nguyen, Pai-Hung Pan
  • Patent number: 5298790
    Abstract: An improved mask and method of forming a deep and width trench in a substrate and the resulting structure is disclosed. A substrate material such as silicon has deposited thereon a first layer of sacrificial material as a first component of an etch mask, the sacrificial material being a material such as polysilicon that is either etched by or absorbs the same ions which reactively ion etch the substrate. A second layer of material, which resists reactive ion etching, such as silicon dioxide, is deposited over the first layer of material as a second component of the etch mask. The silicon dioxide is patterned in the form of the trench to be formed in the substrate. The layer polysilicon material is then reactive ion etched and the reactive ion etching continued to form a trench in the silicon substrate. The polysilicon acts as a sacrificial material being etched by any ions that are reflected from the silicon dioxide or are directed at an angle such that they strike the layer of polysilicon material.
    Type: Grant
    Filed: October 8, 1992
    Date of Patent: March 29, 1994
    Assignee: International Business Machines Corporation
    Inventors: David L. Harmon, Michael L. Kerbaugh, Nancy T. Pascoe, John F. Rembetski
  • Patent number: 5204138
    Abstract: A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride layer on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4.
    Type: Grant
    Filed: December 24, 1991
    Date of Patent: April 20, 1993
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, David M. Dobuzinsky, Douglas J. Dopp, David L. Harmon
  • Patent number: 5118384
    Abstract: An improved mask and method of forming a deep and uniform width trench in a substrate and the resulting structure is disclosed. A substrate material such as silicon has deposited thereon a first layer of sacrificial material as a first component of an etch mask, the sacrificial material being a material such as polysilicon that is either etched by or absorbs the same ions which reactively ion etch the substrate. A second layer of material, which resists reactive ion etching, such as silicon dioxide, is deposited over the first layer of material as a second component of the etch mask. The silicon dioxide is patterned in the form of the trench to be formed in the substrate. The layer polysilicon material is then reactive ion etched and the reactive ion etching continued to form a trench in the silicon substrate. The polysilicon acts as a sacrificial material being etched by any ions that are reflected from the silicon dioxide or are directed at an angle such that they strike the layer of polysilicon material.
    Type: Grant
    Filed: December 10, 1991
    Date of Patent: June 2, 1992
    Assignee: International Business Machines Corporation
    Inventors: David L. Harmon, Michael L. Kerbaugh, Nancy T. Pascoe, John F. Rembetski