Patents by Inventor David L. Kencke

David L. Kencke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9754996
    Abstract: The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Dmitri E. Nikonov, Robert S. Chau
  • Patent number: 9735348
    Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Elijah V. Karpov, Roksana Golizadeh Mojarad, David L. Kencke, Robert S. Chau
  • Patent number: 9728238
    Abstract: Spin transfer torque memory (STTM) devices with half-metals and methods to write and read the devices are described. For example, a magnetic tunneling junction includes a free magnetic layer, a fixed magnetic layer, and a dielectric layer disposed between the free magnetic layer and the fixed magnetic layer. One or both of the free magnetic layer and the fixed magnetic layer includes a half-metal material at an interface with the dielectric layer.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Charles C. Kuo, Roksana Golizadeh Mojarad, Brian S. Doyle, David L. Kencke, Kaan Oguz, Robert S. Chau
  • Publication number: 20170092846
    Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).
    Type: Application
    Filed: July 7, 2014
    Publication date: March 30, 2017
    Applicant: INTEL CORPORATION
    Inventors: BRIAN S. DOYLE, KAAN OGUZ, CHARLES C. KUO, MARK L. DOCZY, SATYARTH SURI, DAVID L. KENCKE, ROBERT S. CHAU, ROKSANA GOLIZADEH MOJARAD
  • Patent number: 9548441
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: January 17, 2017
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Mark L. Doczy, Brian Doyle, Uday Shah, David L. Kencke, Roksana Golizadeh Mojarad, Robert S. Chau
  • Patent number: 9543507
    Abstract: Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less).
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: January 10, 2017
    Assignee: INTEL CORPORATION
    Inventors: Charles Kuo, Elijah V. Karpov, Brian S. Doyle, David L. Kencke, Robert S. Chau
  • Publication number: 20160365385
    Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.
    Type: Application
    Filed: August 25, 2016
    Publication date: December 15, 2016
    Inventors: Ravi PILLARISETTY, Brian S. DOYLE, Elijah V. KARPOV, David L. KENCKE, Uday SHAH, Charles C. KUO, Robert S. CHAU
  • Publication number: 20160359101
    Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.
    Type: Application
    Filed: March 28, 2014
    Publication date: December 8, 2016
    Applicant: INTEL CORPORATION
    Inventors: CHARLES C. KUO, KAAN OGUZ, BRIAN S. DOYLE, MARK L. DOCZY, DAVID L. KENCKE, SATYARTH SURI, ROBERT S. CHAU
  • Publication number: 20160351238
    Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.
    Type: Application
    Filed: March 26, 2014
    Publication date: December 1, 2016
    Applicant: INTEL CORPORATION
    Inventors: BRIAN S. DOYLE, DAVID L. KENCKE, KAAN OGUZ, MARK L. DOCZY, SATYARTH SURI, ROBERT S. CHAU, CHARLES C. KUO, ROKSANA GOLIZADEH MOJARAD
  • Patent number: 9496486
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb
  • Patent number: 9455343
    Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Brian S. Doyle, Elijah V. Karpov, David L. Kencke, Uday Shah, Charles C. Kuo, Robert S. Chau
  • Patent number: 9437808
    Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Charles C. Kuo, David L. Kencke, Roksana Golizadeh Mojarad, Uday Shah
  • Publication number: 20160133829
    Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 12, 2016
    Inventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Elijah V. Karpov, Roksana Golizadeh Mojarad, David L. Kencke, Robert S. Chau
  • Publication number: 20160043302
    Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.
    Type: Application
    Filed: October 19, 2015
    Publication date: February 11, 2016
    Inventors: Brian S. DOYLE, Charles C. KUO, David L. KENCKE, Roksana GOLIZADEH MOJARAD, Uday SHAH
  • Patent number: 9231194
    Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less stable memory having a MTJ with only a single oxide layer. Other embodiments are described herein.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Elijah V. Karpov, Roksana Golizadeh Mojarad, David L. Kencke, Robert S. Chau
  • Patent number: 9214215
    Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 15, 2015
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Kaan Oguz, Satyarth Suri, Robert S. Chau, Charles S. Kuo, Mark L. Doczy, David L. Kencke
  • Publication number: 20150333252
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 19, 2015
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb
  • Patent number: 9166150
    Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Charles C. Kuo, David L. Kencke, Roksana Golizadeh Mojarad, Uday Shah
  • Publication number: 20150243336
    Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
    Type: Application
    Filed: June 10, 2013
    Publication date: August 27, 2015
    Inventors: Elijah V. Karpov, Brian S. Doyle, Kaan Oguz, Satyarth Suri, Robert S. Chau, Charles S. Kuo, Mark L. Doczy, David L. Kencke
  • Patent number: 9105839
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb