Patents by Inventor David M. Fried
David M. Fried has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120205781Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.Type: ApplicationFiled: April 19, 2012Publication date: August 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES INCORPORATEDInventors: David M. Fried, Edward J. Nowak
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Patent number: 8236632Abstract: An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.Type: GrantFiled: October 7, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: David M. Fried, Jeffrey B. Johnson, Kevin McStay, Paul C. Parries, Chengwen Pei, Gan Wang, Geng Wang, Yanli Zhang
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Patent number: 8232624Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.Type: GrantFiled: September 14, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: David M. Fried, Joseph E. Nowak
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Publication number: 20120187490Abstract: A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.Type: ApplicationFiled: March 21, 2012Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: David M. Fried, Jeffrey B. Johnson, Kevin McStay, Paul C. Parries, Chengwen Pei, Gan Wang, Geng Wang, Yanli Zhang
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Publication number: 20120119778Abstract: A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ishtiaq Ahsan, David M. Fried, Lidor Goren, Jiun-Hsin Liao
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Publication number: 20120086077Abstract: An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.Type: ApplicationFiled: October 7, 2010Publication date: April 12, 2012Applicant: International Business Machines CorporationInventors: DAVID M FRIED, Jeffrey B. Johnson, Kevin McStay, Paul C. Parries, Chengwen Pei, Gan Wang, Geng Wang, Yanli Zhang
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Patent number: 7956417Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: GrantFiled: July 20, 2010Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
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Publication number: 20110062555Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.Type: ApplicationFiled: September 14, 2009Publication date: March 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES INCORPORATEDInventors: David M. Fried, Edward J. Nowak
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Patent number: 7884396Abstract: Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.Type: GrantFiled: August 20, 2008Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Gregory Costrini, David M. Fried
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Patent number: 7884411Abstract: An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is connected to the trench electrode, and a second terminal is connected to the active region. The gated diode is operative in one of at least first an second modes as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being greater than the second capacitance.Type: GrantFiled: March 19, 2008Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Leland Chang, Robert H. Dennard, David M. Fried, Wing Kin Luk
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Patent number: 7875550Abstract: Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.Type: GrantFiled: April 28, 2008Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Gregory Costrini, David M. Fried
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Patent number: 7872310Abstract: A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.Type: GrantFiled: January 5, 2009Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Jeffrey S. Brown, David M. Fried, Robert J. Gauthier, Jr., Edward J. Nowak, Jed H. Rankin, William R. Tonti
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Publication number: 20100283089Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: ApplicationFiled: July 20, 2010Publication date: November 11, 2010Applicants: International Business Machines Corporation, GLOBAL FOUNDRIES, INC.Inventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
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Patent number: 7820501Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: GrantFiled: October 11, 2006Date of Patent: October 26, 2010Assignees: International Business Machines Corporation, GlobalFoundries, IncInventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
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Patent number: 7645650Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.Type: GrantFiled: July 9, 2007Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Andres Bryant, Meikei Ieong, K. Paul Muller, Edward J. Nowak, David M. Fried, Jed Rankin
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Publication number: 20090305471Abstract: The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator but thick enough to form a contacting silicide. Stress layer liner films are used both over nFET and pFET device regions to enhance performance.Type: ApplicationFiled: August 14, 2009Publication date: December 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, David M. Fried, John M. Hergenrother, Ghavam Shahidi, Jeffrey W. Sleight
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Publication number: 20090134463Abstract: A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.Type: ApplicationFiled: January 5, 2009Publication date: May 28, 2009Inventors: Wagdi W. Abadeer, Jeffrey S. Brown, David M. Fried, Robert J. Gauthier, JR., Edward J. Nowak, Jed H. Rankin, William R. Tonti
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Patent number: 7517806Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET.Type: GrantFiled: July 21, 2005Date of Patent: April 14, 2009Assignee: International Business Machines CorporationInventors: Andres Bryant, William F. Clark, Jr., David M. Fried, Mark D. Jaffe, Edward J. Nowak, John J. Pekarik, Christopher S. Putnam
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Publication number: 20090090974Abstract: A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile stress liner over an NFET, the NFET including a PFET adjacent thereto; and a compressive stress liner over the PFET, wherein an upper surface of the compressive stress liner is substantially planar with an upper surface of the tensile stress liner at an interface therebetween.Type: ApplicationFiled: October 8, 2007Publication date: April 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory Costrini, David M. Fried, Werner A. Rausch, Christopher D. Sheraw
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Patent number: 7473970Abstract: An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.Type: GrantFiled: July 5, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Jeffrey S. Brown, David M. Fried, Robert J. Gauthier, Jr., Edward J. Nowak, Jed H. Rankin, William R. Tonti