Abstract: Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Serial AT-Attachment (SATA) or integrated device electronics (IDE) PCM solid-state disk or a Multi-Media Card/Secure Digital (MMC/SD) card. A peripheral PCM controller accesses PCM mass storage devices containing PCM memory chips that form a mass-storage device that is block-addressable rather than randomly-addressable. SATA, IDE, or MMC/SD transactions from a host bus are read by a bus transceiver on the peripheral PCM controller. Various routines that execute on a CPU in the peripheral PCM controller are activated in response to commands in the host-bus transactions. A PCM controller in the peripheral controller transfers data from the bus transceiver to the PCM mass storage devices for storage.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data. The very long write-1 time may require wait states. To eliminate wait states for sequential accesses, the PCM cells are divided into 16 banks. Each bank has its own bank write latch that stores data locally at the bank while the bank is being written. Data lines to the banks are freed up to transfer data to other banks once the data is written into the local bank write latch, allowing the long set-current pulse to be applied locally to slowly grow crystals in the alloy resistors. External host data are buffered and applied to the data lines by an array data mux.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The memory cell's reset current can be double a set current, causing peak currents to depend on write data. When all data bits are reset to the amorphous state, a very high peak current is required. To reduce this worst-case peak current, the data is encoded before storage in the PCM cells. An 8/10 encoder adds 2 bits but ensures that no more than half of the data bits are reset. An 8/9 encoder adds an indicator bit, and inverts the 8 bits to ensure that no more than half of the bits are reset. The indicator bit indicates when the 8 bit are inverted, and when the 8 bits are uninverted. Peak currents are thus reduced by encoding to reduce reset data bits.

Abstract: A personal computer motherboard has a main memory of phase-change-memory (PCM) chips in PCM memory modules. An operating system (OS) image is stored in the PCM memory modules and is retained during suspend since the PCM chips are non-volatile. The microprocessor can directly read the OS image retained in the PCM memory modules without copying an OS image from a hard disk to the main memory upon resume. Therefore a boot loader program in the boot ROM does not have to be fetched to the microprocessor for suspend/resume. The video memory can also be PCM, allowing the frame buffer to be retained during suspend/resume, yet be directly addressable by the microprocessor. The display is quickly activated since the frame buffer does not have to be re-constructed after suspend/resume. PCM cells use amorphous and crystalline states of a variable resistor to store data.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

Abstract: An extended Universal-Serial-Bus (USB) connector plug and socket each have a pin substrate with one surface that supports the four metal contact pins for the standard USB interface. An extension of the pin substrate carries another 8 extension metal contact pins that mate when both the connector plug and socket are extended. The extension can be an increased length of the plug's and socket's pin substrate or a reverse side of the substrate. Standard USB connectors do not make contact with the extension metal contacts that are recessed, retracted by a mechanical switch, or on the extension of the socket's pin substrate that a standard USB connector cannot reach. Standard USB sockets do not make contact with the extension metal contacts because the extended connector's extension contacts are recessed, or on the extension of the connector pin substrate that does not fit inside a standard USB socket.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The memory cell's reset current can be double a set current, causing peak currents to depend on write data. When all data bits are reset to the amorphous state, a very high peak current is required. To reduce this worst-case peak current, the data is encoded before storage in the PCM cells. An 8/10 encoder adds 2 bits but ensures that no more than half of the data bits are reset. An 8/9 encoder adds an indicator bit, and inverts the 8 bits to ensure that no more than half of the bits are reset. The indicator bit indicates when the 8 bit are inverted, and when the 8 bits are un-inverted. Peak currents are thus reduced by encoding to reduce reset data bits.

Abstract: Methods and systems of booting an intelligent non-volatile memory (NVM) microcontroller from various sources are described. According to one aspect of the present invention, a NVM microcontroller comprises multiple memory interfaces. Each of the memory interfaces may connect to one of the various sources for booting. The sources may include random access memory (RAM), read-only memory (ROM), Electrically Erasable Programmable ROM (EEPROM) (e.g., NOR flash memory, NAND flash memory). RAM may include static RAM (SRAM), dynamic RAM (DRAM), and synchronous dynamic RAM (SDRAM). Other sources include Secure Digital (SD) card and intelligent non-volatile memory devices. The NAND flash memory may include single-level cell (SLC) flash or multi-level cell (MLC) flash. SLC flash uses a single level per cell or two states per cell, while MLC flash stores four, eight or more states per cell.

Abstract: A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.

Abstract: A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

Abstract: Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array.

Abstract: High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically.

Abstract: Improved reliability high endurance non-volatile memory device with zone-based non-volatile memory file system is described. According to one aspect of the present invention, a zone-based non-volatile memory file system comprises a two-level address mapping scheme: a first level address mapping scheme maps linear or logic address received from a host computer system to a virtual zone address; and a second level address mapping scheme maps the virtual zone address to a physical zone address of a non-volatile memory module. The virtual zone address represents a number of zones each including a plurality of data sectors. Zone is configured as a unit smaller than data blocks and larger than data pages. Each of the data sector consists of 512-byte of data. The ratio between zone and the sectors is predefined by physical characteristics of the non-volatile memory module. A tracking table is used for correlating the virtual zone address with the physical zone address.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives.

Abstract: Portable electronic storage devices with hardware based security are described. According to one exemplary embodiment of the present invention, a portable electronic storage device (PESD) comprises a security engine integrated thereon. The security engine is configured to provide data encryption, data decryption, and encryption/decryption key (referred to as a key) generation according to a security standard (e.g., Advance Encryption Standard (AES)). AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit data block is encrypted by transforming the data block in a unique way into a new data block of the same size. AES is symmetric sine the same key is used for encryption and the reverse transformation (i.e., decryption). The only secret necessary to keep for security is the key. AES may use different key-lengths (i.e., 128-bit, 192-bits and 256-bits).

Abstract: A high volume testing/formatting process is provided for Universal Serial Bus-based (USB-based) electronic data flash cards (USB devices) that meets the increasing demand for USB electronic data flash cards (USB devices). A test host is simultaneously coupled to the multiple USB devices (e.g., using a multi-port card reader or a probe fixture), a controller endpoint value is read from each of the USB devices and verified with a known good value, and then testing/formatting is performed on each of the USB devices by writing predetermined data into each USB device in a pipelined manner, then reading out and testing the predetermined data. In one embodiment, the test host implements a special USB driver that blocks standard USB registration procedures upon detecting the plurality of USB devices. Control and/or boot code data are written onto the flash memory device (i.e., instead of being provided on a controller ROM).

Abstract: An electronic data flash card includes a processor and at least one flash memory device. The flash memory is partitioned such that it includes a first partition that is formatted using a file system that supports an Autorun function (e.g., CD-ROM file system (CDFS) format, fixed-disk format or Universal Disk Format (UDF)), and a disk partition that is formatted using a typical controller-based flash device file system (e.g., 16-bit File Allocation Table (FAT16) file system, 32-bit FAT (FAT32) file system, or New Technology File System (NTFS)). The electronic data flash card is produced such that Autorun-enabled application automatically executes a predetermined application or action when the electronic data flash card is installed in a host system. In one embodiment, the Autorun application includes an advertisement displayed on the host system prior to allowing access to data stored in the disk partition.

Abstract: High performance flash memory devices (FMD) are described. According to one exemplary embodiment of the invention, a high performance FMD includes an I/O interface, a FMD controller, and at least one non-volatile memory module along with corresponding at least one channel controller. The I/O interface is configured to connect the high performance FMD to a host computing device The FMD contoller is configured to control data transfer (e.g., data reading, data writing/programming, and data erasing) operations between the host computing device and the non-volatile memory module. The at least one non-volatile memory module, comprising one or more non-volatile memory chips, is configured as a secondary storage for the host computing device. The at least one channel controller is configured to ensure proper and efficient data transfer between a set of data buffers located in the FMD controller and the at least one non-volatile memory module.

Abstract: An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.