Patents by Inventor David R. Welland

David R. Welland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7203224
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: April 10, 2007
    Assignee: Silicon Laboratories
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 7199650
    Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 3, 2007
    Assignee: Silicon Laboratories Inc.
    Inventors: David R. Welland, Donald A. Kerth, Caiyi Wang
  • Patent number: 7200167
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: April 3, 2007
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 7154940
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: December 26, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 7092675
    Abstract: A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) that generates an output signal. The frequency of the output signal of the VCO circuitry is adjustable in response to a first control signal and a second control signal. The transmitter path circuitry also includes a first feedback circuitry and a second feedback circuitry that are responsive to the output signal of the VCO circuitry. The first feedback circuitry provides the first control signal to the VCO circuitry. The first control signal coarsely adjusts the frequency of the output signal of the VCO circuitry to a desired frequency. The second feedback circuitry supplies the second control signal to the VCO circuitry. The second control signal fine tunes the frequency of the output signal of the voltage-controlled oscillator circuitry to the desired frequency.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: August 15, 2006
    Assignee: Silicon Laboratories
    Inventors: Lysander Lim, Caiyi Wang, David R. Welland, Donald A. Kerth, Richard T. Behrens, Jeffrey W. Scott, G. Diwakar Vishakhadatta, G. Tyson Tuttle, Vishnu S. Srinivasan
  • Patent number: 7084710
    Abstract: An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: August 1, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Yunteng Huang, Bruno W. Garlepp, David R. Welland
  • Patent number: 7072389
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: July 4, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S Sooch, David R. Welland
  • Patent number: 7050509
    Abstract: An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: May 23, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Andrew W. Krone, Timothy J. Dupuis, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 7046755
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: May 16, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 7046793
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end to provide a communication path for signals to and from the phone lines. Briefly described, a means for providing a proper hookswitch transition for a variety of international phone standards is provided. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DAA circuitry may be utilized which satisfies many or all hookswitch transition standards without the use of additional discrete devices. The hookswitch transition standards may be satisfied by ramping down the current flowing through the hookswitch prior to transitioning the hookswitch state. In this manner the hookswitch current change as a function of time (di/dt) may be decreased. Thus, the current through the hookswitch may be actively controlled prior to switching the hookswitch from an off-hook condition to an on-hook condition.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: May 16, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 7003023
    Abstract: An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: February 21, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Andrew W. Krone, Timothy J. Dupuis, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6993314
    Abstract: A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) circuitry. The VCO circuitry generates a first signal that has a first frequency. A divider circuitry couples to the VCO circuitry and, in response to the first signal, the divider circuitry generates a second signal that has a second frequency. The frequency of the second signal equals the frequency of the first signal divided by a number.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: January 31, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Lysander Lim, Caiyi Wang, David R. Welland, Donald A. Kerth, Richard T. Behrens, Jeffrey W. Scott, G. Diwakar Vishakhadatta, G. Tyson Tuttle, Vishnu S. Srinivasan
  • Patent number: 6993307
    Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may include an analog control loop in which a phase detector circuit and sample and hold circuit are utilized. The output of the sample and hold circuit may be provided to the PLL VCO as VCO input control signals.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: January 31, 2006
    Assignee: Silicon Laboratories, Inc.
    Inventors: David R. Welland, Caiyi Wang
  • Patent number: 6975723
    Abstract: A communication system is provided which draws virtually no loop current during a ringing burst and only draws on-hook loop current during the caller ID field. More particularly, ringer burst circuitry may be powered from the user powered circuitry by the transmission of power across the isolation barrier rather than being powered from the phone line. Thus, loop current need not be drawn from the TIP/RING lines during ringer bursts. The isolation barrier may be a capacitive isolation barrier which allows bidirectional communication and extraction of power from signals transmitted across the barrier.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: December 13, 2005
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland, Jerrell P. Hein, Andrew W. Krone
  • Patent number: 6965761
    Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: November 15, 2005
    Assignee: Silicon Laboratories, Inc.
    Inventors: David R. Welland, Caiyi Wang
  • Patent number: 6959083
    Abstract: An audio signal processor which modifies audio signal components outside the conventional audio frequency band. The processor includes a Delta Sigma Modulator (DSM) that receives a non-interpolated digital audio signal sampled at a frequency of at least 198 kHz.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: October 25, 2005
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Andrew W. Krone, Navdeep S. Sooch, David R. Welland
  • Patent number: 6927630
    Abstract: A method and apparatus is provided for detecting the output power of an RF power amplifier for purposes of controlling the output power. A circuit for generating an output power control signal includes a power detector to detect the output power of an RF power amplifier. A variable gain amplifier is coupled to the power detector for amplifying the output of the power detector. The value of the generated control signal is a function of the gain of the variable gain amplifier.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: August 9, 2005
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, David R. Welland, Ali M. Niknejad, Susanne A. Paul
  • Patent number: 6922469
    Abstract: A communication system of the present invention utilizes ring detection circuitry on both sides of an isolation barrier. More particularly, the ring detection circuitry may include ring burst circuitry on the phone line side of the isolation barrier and ringer timing circuits on the powered side of the isolation barrier. The digital burst peak signal may be transmitted through the isolation banier to the finger timing circuits. By splitting the ring detection circuitry so that the ringer timing circuits are placed on the powered side of the isolation barriers, a significant reduction in the power usage on the phone line side of the barrier related to the ring detection function may occur. The outputs of the ringing timing circuits may be provided to circuits on either side of the isolation barrier. Thus, the ring detection function may be accomplished in a system utilizing an efficient bidirectional capacitive barrier while still minimizing power usage on the line side of the barrier.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: July 26, 2005
    Assignee: Silicon Laboratories, Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland, Jerrell P. Hein
  • Patent number: 6917245
    Abstract: A method and apparatus is provided for detecting the output power of a power amplifier. The output power is detected by detecting the absolute values of the voltage and current at the output of the amplifier and mixing the detected voltage and current to generate a signal related to the output power.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: July 12, 2005
    Assignee: Silicon Laboratories, Inc.
    Inventors: Timothy J. Dupuis, David R. Welland, Susanne A. Paul, Ali M. Niknejad
  • Patent number: 6903617
    Abstract: A semiconductor package includes a package substrate and an integrated circuit. The package substrate has a first surface. The integrated circuit couples electrically to the first surface of the package substrate. The integrated circuit and the package substrate together form the semiconductor package. The semiconductor package also includes a first inductance circuit and a second inductance circuit, both formed within the semiconductor package. The first and second inductance circuits couple to each other in parallel. The first and second inductance circuits have substantially symmetrical geometric characteristics.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: June 7, 2005
    Assignee: Silicon Laboratories Inc.
    Inventors: Lysander Lim, David R. Welland, John B. Pavelka, Edmund G. Healy