Patents by Inventor David R. Welland

David R. Welland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040057524
    Abstract: An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.
    Type: Application
    Filed: September 26, 2003
    Publication date: March 25, 2004
    Applicant: Silicon Laboratories Inc.
    Inventors: Andrew W. Krone, Timothy J. Dupuis, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Publication number: 20040046875
    Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 11, 2004
    Inventors: Nadi R. Itani, Caiyi Wang, David R. Welland
  • Patent number: 6683548
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: January 27, 2004
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6654409
    Abstract: An isolation system for terminating a phone line is provided. The invention may comprise a capacitive isolation barrier across which a digital signal is communicated. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. A bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: November 25, 2003
    Assignee: Silicon Laboratories, Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6650364
    Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: November 18, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Nadi R. Itani, Caiyi Wang, David R. Welland
  • Patent number: 6646822
    Abstract: A sampled amplitude read channel incorporated within a magnetic disk storage system for reading data recorded tracks on a magnetic medium, where the data comprises user data sectors recorded at varying data rates across a plurality of predefined zones and embedded servo data sectors recorded at the same data rate across the zones. The read channel comprises a timing recovery component for synchronous sampling of a read signal from a magnetic read head positioned over the magnetic medium, a gain control component for adjusting the amplitude of the read signal, and a DC offset component for canceling a DC offset in the read signal. These components are dynamically configured to operate according to whether the read channel is processing user data or embedded servo data.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: November 11, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Tyson Tuttle, Diwakar Vishakhadatta, Jerrel P. Hein, David R. Welland, David E. Reed, Richard T. Behrens, William G. Bliss, Paul M. Romano, Trent O. Dudley, Christopher P. Zook
  • Publication number: 20030206626
    Abstract: A communication system is provided with a power supply budget such that portions of a phone line side circuit may be powered from the TIP and RING phone lines while using standard electronic devices for the hookswitch circuits and the diode bridge circuit. For example, low voltage converters in the phone line side circuit may be powered from the phone line. The low voltage converters may operate off a low voltage power supply of approximately 2.5 V or less, more preferably may operate off a low voltage power supply of approximately 2.0 V or less, and in one embodiment 1.9 V converters may be utilized. The communication system may further include a capacitive isolation barrier system for isolating the phone line side circuitry.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 6, 2003
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland, Jerrell P. Hein, Andrew W. Krone
  • Publication number: 20030194083
    Abstract: A communication system is provided with a power supply budget such that portions of a phone line side circuit may be powered from the TIP and RING phone lines while using standard electronic devices for the hookswitch circuits and the diode bridge circuit. For example, low voltage converters in the phone line side circuit may be powered from the phone line. The low voltage converters may operate off a low voltage power supply of approximately 2.5 V or less, more preferably may operate off a low voltage power supply of approximately 2.0 V or less, and in one embodiment 1.9 V converters may be utilized. The communication system may further include a capacitive isolation barrier system for isolating the phone line side circuitry.
    Type: Application
    Filed: May 5, 2003
    Publication date: October 16, 2003
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland, Jerrell P. Hein
  • Patent number: 6611553
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: August 26, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6587560
    Abstract: A communication system is provided with a power supply budget such that portions of a phone line side circuit are powered from the TIP and RING phone lines while using standard electronic devices for the hookswitch circuits and the diode bridge circuit. For example, low voltage converters in the phone line side circuit are powered from the phone line. The low voltage converters operate off a low voltage power supply of approximately 2.5 V or less, more preferably operate off a low voltage power supply of approximately 2.0 V or less, and in one embodiment 1.9 V converters are utilized. In one embodiment, the communication system further includes a capacitive isolation barrier system for isolating the phone line side circuitry.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: July 1, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Publication number: 20030119467
    Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock.
    Type: Application
    Filed: February 5, 2003
    Publication date: June 26, 2003
    Applicant: Silicon Laboratories, Inc.
    Inventors: David R. Welland, Caiyi Wang
  • Publication number: 20030107505
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Application
    Filed: January 17, 2003
    Publication date: June 12, 2003
    Applicant: Silicon Laboratories, Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6574288
    Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, discrete control circuitry is disclosed that provides a digital control signal to a discretely variable capacitance circuit to control its overall capacitance and that adjusts the digital control signal depending upon feedback from the output frequency.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: June 3, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: David R. Welland, Caiyi Wang
  • Patent number: 6570513
    Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: May 27, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Publication number: 20030091140
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 15, 2003
    Applicant: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6549765
    Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: April 15, 2003
    Assignee: Silicon Laboratories, Inc.
    Inventors: David R. Welland, Caiyi Wang
  • Patent number: 6549764
    Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, a plurality of connected capacitor circuits for the discretely variable capacitance are disclosed each having a first switch that selectively couples a capacitor between two nodes.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: April 15, 2003
    Assignee: Silicon Laboratories Inc.
    Inventor: David R. Welland
  • Patent number: 6522745
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end to provide a communication path for signals to and from the phone lines. Briefly described, a means for providing a proper ringer impedance for a variety of international phone standards while also providing a proper isolation barrier to the phone line is disclosed. More particularly, a DAA circuitry may be utilized which satisfies many or all ringer impedance standards without the use of additional discrete impedance devices. The ringer impedance standards may be satisfied by use of an impedance structure coupled between the TIP and RING lines and actively controlling the current drawn through the hookswitch devices when a ringing event is detected so as to control the impedance seen at the TIP and RING lines during a ringing event. The detection of the ringing event may be performed on the phone line side of an isolation barrier.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: February 18, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6516024
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors. Further, the current limiting mode includes a distortion adjustment circuit to limit distortion at a crossover point at which current limiting effects occur.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: February 4, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6504864
    Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided that is a second order circuit. The use of a second order circuit provides improved distortion characteristics, particularly at low frequencies.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: January 7, 2003
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, George Tyson Tuttle, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland