Abstract: Methods for identifying hydrocarbon contamination sources may include fingerprinting hydrocarbons using isotopocule analyses for BTEX compounds. For example, methods for identifying hydrocarbon contamination sources may comprise: extracting BTEX compounds from a sample; measuring the isotopocule composition of the BTEX compounds; and determining a characteristic of the sample based on the isotopocule composition. Such characteristics may include, but are not limited to, the characteristic of the sample comprises one or more selected from the group consisting of: a source of the sample, a condition at which the sample formed or was last equilibrated, a migration time from a source to a sample location, weathering of the sample, and degree to which the sample is anthropogenic and naturally-occurring.

Abstract: A quantitative simulation process for producing quantitative model predictions of hydrocarbon composition. The quantitative simulation may include measuring a chemical and isotopic composition of a hydrocarbon sample from a hydrocarbon reservoir.

Abstract: A quantitative simulation process for producing quantitative model predictions of hydrocarbon composition may comprise: measuring a chemical and isotopic composition of a hydrocarbon sample from a hydrocarbon reservoir; measuring geochemical data, geophysical data, and/or geological data for the hydrocarbon reservoir and/or source rock; deriving temperature versus time relationships from a basin model for the hydrocarbon reservoir and/or source rock based on the geochemical data, geophysical data, and/or geological data; generating estimated source-rock maturity parameters based on the temperature versus time relationships; generating an estimated compositional yield for hydrocarbon fractions based on the temperature versus time relationships and the chemical composition of the hydrocarbon sample; and generating, using a mass-conserving isotopic fraction (MCIF) simulator, an estimated isotopic composition of the hydrocarbon fractions based on the estimated compositional yield and the isotopic composition of t

Abstract: Methods for identifying hydrocarbon contamination sources may include fingerprinting hydrocarbons using isotopocule analyses for BTEX compounds. For example, methods for identifying hydrocarbon contamination sources may comprise: extracting BTEX compounds from a sample; measuring the isotopocule composition of the BTEX compounds; and determining a characteristic of the sample based on the isotopocule composition. Such characteristics may include, but are not limited to, the characteristic of the sample comprises one or more selected from the group consisting of: a source of the sample, a condition at which the sample formed or was last equilibrated, a migration time from a source to a sample location, weathering of the sample, and degree to which the sample is anthropogenic and naturally-occurring.

Abstract: A device includes a connector and a detector device. The connector includes at least one first-type pin and at least one second-type pin. The connector is capable of being connected to a corresponding connector of a solid-state drive (SSD) device. The detector device controls the at least one first-type pin to be coupled to a first power supply voltage based on, at least in part, the at least one second-type pin is connected to a second power supply voltage while the corresponding connector of the SSD device is connected to the first connector. If the at least one second-type pin is detected as being connected to a third power supply voltage different from the second power supply voltage while the corresponding connector of the SSD device is connected to the first connector, the detector device controls the at least one first-type pin to be in a non-connected state.

Abstract: A device includes a connector and a detector device. The connector includes at least one first-type pin and at least one second-type pin. The connector is capable of being connected to a corresponding connector of a solid-state drive (SSD) device. The detector device controls the at least one first-type pin to be coupled to a first power supply voltage based on, at least in part, the at least one second-type pin is connected to a second power supply voltage while the corresponding connector of the SSD device is connected to the first connector. If the at least one second-type pin is detected as being connected to a third power supply voltage different from the second power supply voltage while the corresponding connector of the SSD device is connected to the first connector, the detector device controls the at least one first-type pin to be in a non-connected state.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract: A method for manufacturing a dynamic random access memory device is provided. The method includes fabricating a dynamic random access memory device having a plurality of memory cells. Each of the memory cells has a refresh characteristic that meets or exceeds a refresh specification provided for a DDR3 SDRAM device or a DDR4 SDRAM device. The method includes testing the dynamic random access memory device. The testing includes determining the refresh characteristic for each of the memory cells, classifying each of the memory cells as a good memory cell or a bad memory cell based upon the refresh characteristic, identifying each of the bad memory cells, and storing an address location for each of the bad memory cells. The method then includes transferring the address location for each of the bad memory cells into an address match table.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: An integrated circuit memory interface device coupled to a dynamic random access memory device is provided. The device includes an address match table. The address match table includes a plurality of first addresses. Each of the first addresses is associated with a memory cell having a refresh characteristic outside of a specification for a DRAM device. The device has a plurality of second addresses. Each of the second addresses is associated with a refresh characteristic within a specification of the DRAM device and outside of a predetermined refresh characteristic range characterized to eliminate accesses to memory cells not meeting the predetermined refresh characteristic range.

Abstract: A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed.

Abstract: A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.