Patents by Inventor David T. Wang

David T. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY DEVICE WITH EMULATED CHARACTERISTICS
    Publication number: 20080126687
    Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY DEVICE WITH EMULATED CHARACTERISTICS
    Publication number: 20080126689
    Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY DEVICE WITH EMULATED CHARACTERISTICS
    Publication number: 20080126688
    Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY DEVICE WITH EMULATED CHARACTERISTICS
    Publication number: 20080126692
    Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS
    Publication number: 20080120443
    Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 22, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • SYSTEM AND METHOD FOR ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM
    Publication number: 20080115006
    Abstract: A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.
    Type: Application
    Filed: November 13, 2007
    Publication date: May 15, 2008
    Inventors: Michael John Sebastian Smith, Daniel L. Rosenband, David T. Wang, Suresh Natarajan Rajan
  • APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF
    Publication number: 20080082763
    Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 3, 2008
    Inventors: Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang
  • SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT
    Publication number: 20080062773
    Abstract: A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.
    Type: Application
    Filed: June 12, 2007
    Publication date: March 13, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY DEVICE WITH EMULATED CHARACTERISTICS
    Publication number: 20080056014
    Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
    Type: Application
    Filed: June 12, 2007
    Publication date: March 6, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS
    Publication number: 20080031072
    Abstract: A power saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accesses. In response to the identification of the at least one memory circuit, a power saving operation is initiated in association with the at least one memory circuit.
    Type: Application
    Filed: July 31, 2006
    Publication date: February 7, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • System and method for power management in memory systems
    Publication number: 20080031030
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.
    Type: Application
    Filed: September 20, 2006
    Publication date: February 7, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION
    Publication number: 20080025136
    Abstract: A system and method are provided for use in the context of a plurality of memory circuits. In use, first information is received in association with a first operation to be performed on at least one of the memory circuits. At least a portion of the first information is stored. Still yet, second information is received in association with a second operation to be performed on at least one of the plurality of memory circuits. To this end, the second operation may be performed utilizing the stored portion of the first information in addition to the second information.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MULTIPLE-COMPONENT MEMORY INTERFACE SYSTEM AND METHOD
    Publication number: 20080028135
    Abstract: A system and method are provided, wherein a first component and a second component are operable to interface a plurality of memory circuits and a system.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • SYSTEM AND METHOD FOR DELAYING A SIGNAL COMMUNICATED FROM A SYSTEM TO AT LEAST ONE OF A PLURALITY OF MEMORY CIRCUITS
    Publication number: 20080025108
    Abstract: A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH POWER SAVING CAPABILITIES
    Publication number: 20080027697
    Abstract: A system and method are provided including a component in communication with a plurality of memory circuits and a system. The component is operable to interface the memory circuits an the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The component is further operable to perform a power saving operation.
    Type: Application
    Filed: October 26, 2006
    Publication date: January 31, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT
    Publication number: 20080025137
    Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
    Publication number: 20080025123
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.
    Type: Application
    Filed: September 20, 2006
    Publication date: January 31, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY REFRESH SYSTEM AND METHOD
    Publication number: 20080025122
    Abstract: A system and method are provided. In response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: Keith R. Schakel, Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Interface circuit system and method for performing power management operations utilizing power management signals
    Publication number: 20080025124
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.
    Type: Application
    Filed: September 20, 2006
    Publication date: January 31, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Method and Apparatus For Refresh Management of Memory Modules
    Publication number: 20080028137
    Abstract: One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices
    Type: Application
    Filed: July 25, 2007
    Publication date: January 31, 2008
    Inventors: Keith R. Schakel, Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang