Abstract: A system and method are provided including an interface circuit in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the plurality of memory circuits and the system for simulating at leas one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The interface circuit is further operable to control refreshing of the plurality of memory circuits.

Abstract: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system.

Abstract: A system and method are provided for simulating a different number of memory circuits. Included is an interface circuit in communication with a first number of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number. Further, the interface circuit interfaces a majority of address or control signals of the memory circuits.

Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits.

Abstract: A distributed data processing system includes plural, processor-containing nodes that are interconnected in a network. Each node has plural neighbor nodes, with neighbor nodes being connected via a direct link. One node includes a copy of functional microcode in addition to base microcode. Each node further includes memory for storing base microcode which enables, on power-up, for a processor in the node to manifest partial operational capability, including program load functions and a communications capability with neighbor nodes. The node's processor, in combination with the base microcode, determines if the node's memory stores a copy of functional microcode and if yes, causes the functional microcode to be loaded. If it is determined that functional microcode is not present in the nodes memory, the node issues a request to neighbor nodes to download functional code, irrespective of whether the neighbor node's are known to include the functional microcode or not.

Abstract: Updating of control code is accomplished in multiple nodes of a computing system while the computing system remains in operation. Each node includes a processor, memory, a first version of a control code unit and an engineering change level indication for the control code unit. The method comprises the steps of: installing a revised version of the control code unit with converter code modules in a first node, the converter code modules enabling and performing first and second interface functions during communications between the first node and other nodes in the system. The first node is then operated to perform a function which requires communication with other nodes, the converter code module in the first node initially determining an engineering change level value stored in another node and, if the engineering change level values in the nodes match, communicating with the other node through the first interface function.

Abstract: In a data processing system in which two-level error correction is performed on variable length data being transferred between the host processor and the data storage device, the logical length of the data being transferred is computed during a fixed time gap with computation continuing after termination of the fixed time gap and commencement of the data transfer. The computation required for the logical length of the data field to accommodate two-level ECC is accomplished by first comparing the actual field length with a value predetermined by the subblock length of the two-level ECC. If the actual length is greater than the predetermined value, then a value equal to the subblock length plus first level ECC bytes is loaded into a counter which begins decrementing at the termination of the fixed time gap so as to synhronize by the byte-by-byte transfer of the data. As the data is being transferred the computation continues.

Abstract: Disclosed is a method for recording a record that emulates a first recording format, which includes a track reference point, such as an index field, used for determining a position of a record on a track according to the first recording format, on a moving storage device operating according to a second recording format which also includes a track reference point. The invention comprises the steps, responsive to location information generated according to the first recording formats, of:(1) determining an original angular position of a record according to the first recording format;(2) calculating in response to the original angular position and a parameter a preferred angular position for the record according to the second recording format;(3) determining an actual angular position of the record recorded according to the second recording format; and(4) recording an extension of the record to compensate for the difference between the preferred angular position and the actual angular position.

Abstract: A page modification method in a printer subsystem of the partial page buffer composing type. A printer subsystem receives a packet containing a page of characters, coded overlays/elisions, and combining data from an external source. The packet is translated into a linked list of character placement representations for each of the doubly indexed coded characters within the page. Elisions from the page are made by inhibiting the formation of a linked list segment for each character sequence within elision markers set out in the page. In contrast, coded character overlays are appended to the list as addenda. The list governs the placement of characters into a partial page buffer, whose contents are system accessible in row major order.

Abstract: Mechanical digital lock operable through a series of mechanical operations actuated by the depression of digital keys comprises an intellectual combination of essential mechanisms including a plurality of keys, digital selectors, identifiers, locking means and automatic resets. The lock cannot be opened unless the predetermined digitals are sequentially depressed. Once the lock is opened, it is automatically reset. A change of combination of digitals can easily be manually effected without any tool. With its novel structure, it is highly reliable.