Patents by Inventor David V. Caletka
David V. Caletka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7875811Abstract: A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.Type: GrantFiled: January 24, 2008Date of Patent: January 25, 2011Assignee: Endicott Interconnect Technologies, Inc.Inventors: David V. Caletka, Frank D. Egitto
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Patent number: 7629541Abstract: A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.Type: GrantFiled: June 19, 2006Date of Patent: December 8, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: David V. Caletka, Frank D. Egitto
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Patent number: 7510912Abstract: A method of making a wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for the chip during operation thereof and may operate in combination with other elements to extend the heat paths. Concentric lines also assure sufficient bonding area on the substrate so as to prevent delamination of the chip from the substrate as may occur during high temperatures associated with subsequent processing such as solder ball re-flow.Type: GrantFiled: July 9, 2007Date of Patent: March 31, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: David V. Caletka, Varaprasad V. Calmidi, Sanjeev Sathe
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Patent number: 7499614Abstract: A method of producing opto-electronic cards and printed circuit boards which are adapted to provide for passive alignment of VCSELs to waveguides. Also provided are opto-electronic cards and printed circuit boards which incorporate structure providing for the passive alignment of VCSELs to waveguides.Type: GrantFiled: October 24, 2003Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Eric A. Johnson, David V. Caletka
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Publication number: 20080142258Abstract: A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.Type: ApplicationFiled: January 24, 2008Publication date: June 19, 2008Applicant: Endicott Interconnect Technologies, Inc.Inventors: David V, Caletka, Frank D. Egitto
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Publication number: 20080120835Abstract: A method of making a high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.Type: ApplicationFiled: January 25, 2008Publication date: May 29, 2008Applicant: Endicott Interconnect Technologies, Inc.Inventors: David V. Caletka, Frank D. Egitto
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Publication number: 20070289773Abstract: A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.Type: ApplicationFiled: June 19, 2006Publication date: December 20, 2007Applicant: Endicott Interconnect Technologies, Inc.Inventors: David V. Caletka, Frank D. Egitto
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Patent number: 7253518Abstract: A wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for the chip during operation thereof and may operate in combination with other elements to extend the heat paths. Concentric lines also assure sufficient bonding area on the substrate so as to prevent delamination of the chip from the substrate as may occur during high temperatures associated with subsequent processing such as solder ball re-flow. A method of making the package is also provided, as is an information handling system (e.g., computer) adapted for utilizing such packages.Type: GrantFiled: June 15, 2005Date of Patent: August 7, 2007Assignee: Endicott Interconnect Technologies, Inc.Inventors: David V. Caletka, Varaprasad V. Calmidi, Sanjeev Sathe
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Patent number: 6933619Abstract: An electronic package and method of making same in which a thermally conductive member is in thermally conductive communication with a semiconductor chip encapsulated within a dielectric material that surrounds portions of a thermally conductive member, semiconductor chip, and a predefined portion of a circuitized substrate. The present invention's thermally conductive member includes two portions of different bending stiffness to assure reduced interfacial stresses between the semiconductor chip and the circuitized substrate.Type: GrantFiled: October 18, 2002Date of Patent: August 23, 2005Assignee: International Business Machines CorporationInventors: David V. Caletka, Eric A. Johnson
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Patent number: 6913948Abstract: A Ball Grid Array package having an increased fatigue life and improved conductive pad adhesion strength, as well as providing sufficient wiring space within the package, is disclosed. In particular, solder joints having a combination of mask-defined and pad-defined solder joint profiles are formed using a mask having non-circular elongated openings. The non-circular elongated openings of the mask have a major axis and a minor axis, such that the dimension of the openings along the major axis is greater than the diameter of the conductive pads, and the dimension of the openings along the minor axis is less than the diameter of the conductive pads. In addition, the major axis of the openings within the mask are selectively oriented in the direction of highest stress for each solder joint within the package, while providing ample wiring space therein.Type: GrantFiled: November 20, 2003Date of Patent: July 5, 2005Assignee: International Business Machines CorporationInventors: David V. Caletka, Eric A. Johnson
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Patent number: 6774474Abstract: A Ball Grid Array package having an increased fatigue life and improved conductive pad adhesion strength, as well as providing sufficient wiring space within the package, is disclosed. In particular, solder joints having a combination of mask-defined and pad-defined solder joint profiles are formed using a mask having non-circular elongated openings. The non-circular elongated openings of the mask have a major axis and a minor axis, such that the dimension of the openings along the major axis is greater than the diameter of the conductive pads, and the dimension of the openings along the minor axis is less than the diameter of the conductive pads. In addition, the major axis of the openings within the mask are selectively oriented in the direction of highest stress for each solder joint within the package, while providing ample wiring space therein.Type: GrantFiled: November 10, 1999Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: David V. Caletka, Eric A. Johnson
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Publication number: 20040099936Abstract: A Ball Grid Array package having an increased fatigue life and improved conductive pad adhesion strength, as well as providing sufficient wiring space within the package, is disclosed. In particular, solder joints having a combination of mask-defined and pad-defined solder joint profiles are formed using a mask having non-circular elongated openings. The non-circular elongated openings of the mask have a major axis and a minor axis, such that the dimension of the openings along the major axis is greater than the diameter of the conductive pads, and the dimension of the openings along the minor axis is less than the diameter of the conductive pads. In addition, the major axis of the openings within the mask are selectively oriented in the direction of highest stress for each solder joint within the package, while providing ample wiring space therein.Type: ApplicationFiled: November 20, 2003Publication date: May 27, 2004Inventors: David V. Caletka, Eric A. Johnson
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Patent number: 6695623Abstract: A method and structure for electrically and mechanically interconnecting an array of printed circuit board contacts to an array of module contacts with a plurality of deformable resilient electrical conductors with two ends. Each of the conductor ends are electrically connected to one of the contact arrays. A portion of the conductor may deform longitudinally and laterally responsive to movement of the printed circuit board relative to the module responsive to heating and cooling cycles and mechanical vibrations, while maintaining the electrical connection of the contact arrays. An interposer with apertures extending through the interposer carries the conductors in the apertures and is used to align the conductors with the contacts. A method for excluding a rigid adhesive means from a portion of the resilient conductor is also taught.Type: GrantFiled: May 31, 2001Date of Patent: February 24, 2004Assignee: International Business Machines CorporationInventors: William Louis Brodsky, David V. Caletka, Michael Anthony Gaynes, Voya Rista Markovich
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Patent number: 6672500Abstract: A method and an arrangement for measuring the cooling rate and temperature differential between the top and bottom surfaces of a printed circuit board. The method is intended to facilitate control over the temperature differential which is encountered between the top and bottom of the printed circuit board so as to prevent warpage thereof during the formation of solder joints in a reflow solder oven.Type: GrantFiled: March 7, 2001Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: David V. Caletka, Kevin Knadle, Charles G. Woychik
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Patent number: 6649833Abstract: An electronic package is provided including a substrate, a device mounted on the substrate, and a solder member electrically coupling the device to the substrate. The package includes a dielectric material positioned substantially around the solder member which forms a physical connection between the substrate and the device. The volume of the solder member contracts during melting thereof to prevent failure of the physical connection and/or the electrical coupling between the substrate and the device.Type: GrantFiled: August 9, 2002Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: David V. Caletka, Krishna Darbha, Donald W. Henderson, Lawrence P. Lehman, George H. Thiel
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Patent number: 6603195Abstract: A semiconductor module includes a semiconductor chip, a lead frame having lead fingers, and a down set member within an encapsulant for reduce warpage and providing a more planar package by balancing thermal stress between the lead fingers and the encapsulant. The down set member can be a bent portion of the lead frame. It can also be a separate body, such as a dummy semiconductor chip.Type: GrantFiled: June 28, 2000Date of Patent: August 5, 2003Assignee: International Business Machines CorporationInventors: David V. Caletka, James L. Carper, John P. Cincotta, Kibby B. Horsford, Gary H. Irish, John J. Lajza, Jr., Gordon C. Osborne, Jr., Charles R. Ramsey, Robert M. Smith, Michael J. Vadnais
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Patent number: 6541857Abstract: A method of forming BGA interconnections having improved fatigue life is disclosed. In particular, a combination of mask-defined and pad-defined solder joints are selectively positioned within the BGA package. The mask-defined solder joints possess a high equilibrium height, which forces the pad-defined solder joints to elongate, thereby making the pad-defined solder joints more compliant. Further, the pad-defined solder joints possess a slightly longer fatigue life because the stress concentrations found in the mask-defined solder joints are not present in the pad-defined solder joints. Therefore, the fatigue life of BGA packages is increased by implementing a majority of mask-defined solder joints to maintain a high equilibrium height, and selectively placing pad-defined solder joints in high stress areas of the BGA package.Type: GrantFiled: January 4, 2001Date of Patent: April 1, 2003Assignee: International Business Machines CorporationInventors: David V. Caletka, Eric A. Johnson
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Publication number: 20030034569Abstract: An electronic package and method of making same in which a thermally conductive member is in thermally conductive communication with a semiconductor chip encapsulated within a dielectric material that surrounds portions of a thermally conductive member, semiconductor chip, and a predefined portion of a circuitized substrate. The present invention's thermally conductive member includes two portions of different bending stiffness to assure reduced interfacial stresses between the semiconductor chip and the circuitized substrate.Type: ApplicationFiled: October 18, 2002Publication date: February 20, 2003Applicant: International Business Machines CorporationInventors: David V. Caletka, Eric A. Johnson
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Patent number: 6507116Abstract: An electronic package and method of making same in which a thermally conductive member is in thermally conductive communication with a semiconductor chip encapsulated within a dielectric material that surrounds portions of a thermally conductive member, semiconductor chip, and a predefined portion of a circuitized substrate. The present invention's thermally conductive member includes two portions of different bending stiffness to assure reduced interfacial stresses between the semiconductor chip and the circuitized substrate.Type: GrantFiled: October 29, 1999Date of Patent: January 14, 2003Assignee: International Business Machines CorporationInventors: David V. Caletka, Eric A. Johnson
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Publication number: 20020182900Abstract: A method and structure for electrically and mechanically interconnecting an array of printed circuit board contacts to an array of module contacts with a plurality of deformable resilient electrical conductors with two ends. Each of the conductor ends are electrically connected to one of the contact arrays. A portion of the conductor may deform longitudinally and laterally responsive to movement of the printed circuit board relative to the module responsive to heating and cooling cycles and mechanical vibrations, while maintaining the electrical connection of the contact arrays. An interposer with apertures extending through the interposer carries the conductors in the apertures and is used to align the conductors with the contacts. A method for excluding a rigid adhesive means from a portion of the resilient conductor is also taught.Type: ApplicationFiled: May 31, 2001Publication date: December 5, 2002Applicant: International Business Machines CorporationInventors: William Louis Brodsky, David V. Caletka, Michael Anthony Gaynes, Voya Rista Markovich