Patents by Inventor David W. Sherrer

David W. Sherrer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11196184
    Abstract: Antenna arrays, including a broadband single or dual polarized, tightly coupled radiator arrays.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 7, 2021
    Assignee: Cubic Corporation
    Inventors: Jared W Jordan, Kenneth J Vanhille, Timothy A Smith, William Stacy, Benjamin L Cannon, David W Sherrer
  • Publication number: 20210203085
    Abstract: Antenna arrays, including a broadband single or dual polarized, tightly coupled radiator arrays.
    Type: Application
    Filed: June 19, 2018
    Publication date: July 1, 2021
    Inventors: Jared W Jordan, Kenneth J Vanhille, Timothy A Smith, William Stacy, Benjamin L Cannon, David W Sherrer
  • Patent number: 10431521
    Abstract: Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 1, 2019
    Assignee: CUBIC CORPORATION
    Inventors: Jean-Marc Rollin, David W. Sherrer
  • Publication number: 20190013561
    Abstract: Provided are coaxial waveguide microstructures. The microstructures include a substrate and a coaxial waveguide disposed above the substrate. The coaxial waveguide includes: a center conductor; an outer conductor including one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and enclosed within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state. Also provided are methods of forming coaxial waveguide microstructures by a sequential build process and hermetic packages which include a coaxial waveguide microstructure.
    Type: Application
    Filed: August 21, 2018
    Publication date: January 10, 2019
    Inventors: David W. Sherrer, John J. Fisher
  • Publication number: 20180319108
    Abstract: The present invention relates to the fabrication of complicated electronic and/or mechanical structures and devices and components using homogeneous or heterogeneous 3D additive build processes. In particular the invention relates to selective metallization processes including electroless and/or electrolytic metallization.
    Type: Application
    Filed: June 7, 2018
    Publication date: November 8, 2018
    Inventors: David W. Sherrer, Dara L. Cardwell
  • Patent number: 10076042
    Abstract: Structures, materials, and methods to control the spread of a solder material or other flowable conductive material in electronic and/or electromagnetic devices are provided.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: September 11, 2018
    Assignee: NUVOTRONICS, INC
    Inventors: David W. Sherrer, James R. Reid
  • Patent number: 10074885
    Abstract: Provided are coaxial waveguide microstructures. The microstructures include a substrate and a coaxial waveguide disposed above the substrate. The coaxial waveguide includes: a center conductor; an outer conductor including one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and enclosed within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state. Also provided are methods of forming coaxial waveguide microstructures by a sequential build process and hermetic packages which include a coaxial waveguide microstructure.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: September 11, 2018
    Assignee: NUVOTRONICS, INC
    Inventors: David W. Sherrer, John J. Fisher
  • Patent number: 10002818
    Abstract: Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 19, 2018
    Assignee: Nuvotronics, Inc.
    Inventors: Jean-Marc Rollin, David W. Sherrer
  • Patent number: 9993982
    Abstract: The present invention relates to the fabrication of complicated electronic and/or mechanical structures and devices and components using homogeneous or heterogeneous 3D additive build processes. In particular the invention relates to selective metallization processes including electroless and/or electrolytic metallization.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: June 12, 2018
    Assignee: NUVOTRONICS, INC.
    Inventors: David W. Sherrer, Dara L. Cardwell
  • Publication number: 20180082923
    Abstract: Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 22, 2018
    Inventors: Jean-Marc Rollin, David W. Sherrer
  • Publication number: 20180074272
    Abstract: Method of making an optoelectronic device package.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 15, 2018
    Inventor: David W Sherrer
  • Patent number: 9817199
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: November 14, 2017
    Assignee: NUVOTRONICS, INC
    Inventor: David W Sherrer
  • Publication number: 20170235066
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventor: David W Sherrer
  • Publication number: 20170170592
    Abstract: Connectors and interconnects for high power connectors which may operate at frequencies up to approximately 110 GHz and fabrication methods thereof are provided.
    Type: Application
    Filed: January 12, 2017
    Publication date: June 15, 2017
    Inventors: David W. Sherrer, Jean-Marc Rollin
  • Patent number: 9647420
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: May 9, 2017
    Assignee: Nuvotronics, Inc.
    Inventor: David W Sherrer
  • Patent number: 9583856
    Abstract: Connectors and interconnects for high power connectors which may operate at frequencies up to approximately 110 GHz and fabrication methods thereof are provided.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: February 28, 2017
    Assignee: Nuvotronics, Inc.
    Inventors: David W. Sherrer, Jean-Marc Rollin
  • Publication number: 20170055348
    Abstract: Structures, materials, and methods to control the spread of a solder material or other flowable conductive material in electronic and/or electromagnetic devices are provided.
    Type: Application
    Filed: November 2, 2016
    Publication date: February 23, 2017
    Inventors: David W. Sherrer, James R. Reid
  • Patent number: 9570787
    Abstract: Disclosed and claimed herein is a hollow core coaxial cable, having a dielectric capillary with an inside wall and an outside wall, an inner conductive layer on the inside wall of the hollow core coaxial cable and an outer conductive layer on the outside wall of the hollow core coaxial cable, the conductive layers may be patterned. Further disclosed is a method of making the hollow core coaxial cable. Further disclosed are holey fiber coaxial cables, having a holey fiber capillary having an inside wall and an outside wall, an inner conductive layer on the inside wall of the hollow core coaxial cable and an outer conductive layer on the outside wall of the hollow core coaxial cable, the conductive layers may be patterned.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: February 14, 2017
    Assignee: Nuvotronics, Inc.
    Inventors: David W. Sherrer, Noel Heiks
  • Patent number: 9515364
    Abstract: Provided are three-dimensional microstructures and their methods of formation. The microstructures are formed by a sequential build process and include microstructural elements which are affixed to one another. The microstructures find use, for example, in coaxial transmission lines for electromagnetic energy.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: December 6, 2016
    Assignee: Nuvotronics, Inc.
    Inventors: William D. Houck, David W. Sherrer
  • Patent number: 9505613
    Abstract: Structures, materials, and methods to control the spread of a solder material or other flowable conductive material in electronic and/or electromagnetic devices are provided.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 29, 2016
    Assignee: NUVOTRONICS, INC.
    Inventors: David W. Sherrer, James R. Reid