Patents by Inventor David William Boerstler
David William Boerstler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7620126Abstract: A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.Type: GrantFiled: September 27, 2005Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: David William Boerstler, Matthew E. Fernsler, Eskinder Hailu, Jieming Qi, Mack Wayne Riley
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Patent number: 7617059Abstract: The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.Type: GrantFiled: October 31, 2007Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Jieming Qi
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Patent number: 7595675Abstract: The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.Type: GrantFiled: May 1, 2006Date of Patent: September 29, 2009Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Jieming Qi
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Patent number: 7590194Abstract: An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.Type: GrantFiled: September 27, 2005Date of Patent: September 15, 2009Assignee: International Business Machines CorporationInventors: David William Boerstler, Matthew E. Fernsler, Eskinder Hailu, Jieming Qi, Mack Wayne Riley
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Patent number: 7589575Abstract: A loop filter in a phase lock loop circuit comprising a reference precision resistor, a first FET and a second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and to the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.Type: GrantFiled: October 24, 2007Date of Patent: September 15, 2009Assignee: International Business Machines CorporationInventors: David William Boerstler, Jieming Qi
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Publication number: 20090174468Abstract: Methods, systems and thermal sensing apparatus are provided that use bandgap voltage reference generators that do not use trimming circuitry. Further, circuits, systems, and methods in accordance with the present invention are provided that do not use large amounts of chip real estate and do not require a separate thermal sensing element.Type: ApplicationFiled: March 11, 2009Publication date: July 9, 2009Applicants: Toshiba American Electronic Components, Inc., International Business Machines CorporationInventors: Munehiro Yoshida, David William Boerstler
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Publication number: 20090108924Abstract: A design structure of a circuit for managing voltage swings across FETs comprising a reference precision resistor, a first and second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first and third FETs maintain a linear relationship with respective drain to source voltages of the first and third FETs.Type: ApplicationFiled: May 29, 2008Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David William Boerstler, Jieming Qi
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Publication number: 20090108889Abstract: A loop filter in a phase lock loop circuit comprising a reference precision resistor, a first FET and a second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and to the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.Type: ApplicationFiled: October 24, 2007Publication date: April 30, 2009Inventors: David William Boerstler, Jieming Qi
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Publication number: 20090112555Abstract: A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store.Type: ApplicationFiled: December 31, 2008Publication date: April 30, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM CorporationInventors: David William Boerstler, Eskinder Hailu, Jieming Qi
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Publication number: 20090108923Abstract: A design structure for a loop filter in a phase lock loop circuit comprising a reference precision resistor, a first and second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.Type: ApplicationFiled: May 29, 2008Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David William Boerstler, Jieming Qi
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Publication number: 20090108922Abstract: A circuit for managing voltage swings across FETs comprising a reference precision resistor, a first FET and a second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first FET and the third FET maintain a linear relationship with respective drain to source voltages of the first FET and the third FET.Type: ApplicationFiled: May 29, 2008Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David William Boerstler, Jieming Qi
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Patent number: 7524108Abstract: Methods, systems and thermal sensing apparatus are provided that use bandgap voltage reference generators that do not use trimming circuitry. Further, circuits, systems, and methods in accordance with the present invention are provided that do not use large amounts of chip real estate and do not require a separate thermal sensing element.Type: GrantFiled: May 20, 2003Date of Patent: April 28, 2009Assignees: Toshiba American Electronic Components, Inc., International Business Machines CorporationInventors: Munehiro Yoshida, David William Boerstler
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Publication number: 20080301503Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.Type: ApplicationFiled: August 7, 2008Publication date: December 4, 2008Inventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Patent number: 7453293Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.Type: GrantFiled: August 29, 2006Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Publication number: 20080272820Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.Type: ApplicationFiled: June 4, 2008Publication date: November 6, 2008Applicant: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Mack Wayne Riley, Michael Fan Wang
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Method to reduce transient current swings during mode transitions of high frequency/high power chips
Patent number: 7430264Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.Type: GrantFiled: November 4, 2004Date of Patent: September 30, 2008Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Mack Wayne Riley, Michael Fan Wang -
Patent number: 7420400Abstract: The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.Type: GrantFiled: May 1, 2006Date of Patent: September 2, 2008Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Jieming Qi
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Publication number: 20080174345Abstract: The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.Type: ApplicationFiled: October 31, 2007Publication date: July 24, 2008Applicant: IBM CorporationInventors: David William Boerstler, Eskinder Hailu, Jieming Qi
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Patent number: 7392419Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.Type: GrantFiled: June 30, 2005Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Kazuhiko Miki, Jieming Qi
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Publication number: 20080143419Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.Type: ApplicationFiled: February 25, 2008Publication date: June 19, 2008Inventors: David William Boerstler, Eskinder Hailu, Kazuhiko Miki, Jieming Qi