Abstract: The present invention provides for state correction. A first flip flop coupled to a second flip flop. A state correction circuit coupled to the output of the second flip flop. A third flip flop is coupled to the output of the state correction circuit. A fourth flip flop is coupled to the output of the third flip flop.

Abstract: A method and an apparatus for testing a phase-locked loop (PLL) are provided. A fixed-level reference clock signal and a test feedback clock signal are applied to a phase-frequency detector (PFD) of the PLL to measure a minimum output frequency of a voltage-controlled oscillator (VCO) of the PLL. A test reference clock signal and a fixed-level feedback clock signal are applied to the PFD to measure a maximum output frequency of the VCO. The lock and capture range of the PLL is determined based on the maximum and minimum frequencies of the VCO.

Abstract: A system and method for reducing timing uncertainties in a serial data signal A system may comprise a transmitter configured to transmit serial data to a receiver through a transmission medium, e.g., wireless, wired. The receiver may comprise an oscillator configured to generate multiple phases of a clock. The receiver may further comprise a retiming mechanism configured to reduce the timing uncertainties of the serial data received by the receiver by selecting a particular phase of the clock to be asserted to sample the serial data signal. The particular phase may be selected by selecting the appropriate synchronization state/retiming state. A retiming state indicates which particular phase of the clock should be asserted to sample the serial data signal. A synchronization state indicates which particular phase of the clock is the appropriate one to assert at a given transition of the serial data signal.

Abstract: A lock detector and method is provided for detecting lock between first and second signals. The lock detector includes a pulse generator for receiving the first signal and generating a pulse train from the first signal. Each pulse corresponds to at least one of rising and falling edges of the first signal in each period of the first signal. The lock detector also includes a mask generator for generating a mask signal from the second signal such that the mask signal has a mask state around at least one of rising and falling edges of the second signal in each period of the second signal. Additionally, the lock detector has a logic gate, which receives the pulse train and the mask signal from the pulse generator and the mask generator, respectively. The logic gate generates an incrementing pulse signal by combining the pulse train with the mask signal.

Abstract: A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger to separate “ones” and “zeros” one-shots. The equalized Manchester data signal is also integrated, compared with a threshold value to determine the negative and positive peaks of the data signal. Then after the appropriate peak is determined, a mid-bit signal is sent as input to a set-reset flip-flop which thereby outputs an asynchronous recovered non-return to zero signal. This asynchronous recovered non-return to zero signal then provides an enable input to the “ones” one-shot and the complementary asynchronous recovered non-return to zero signal provides an enable input to the “zeros” one-shot. The “ones” one-shot outputs a “ones” clock signal and the “zeros” one-shot outputs a “zeros” clock signal. These two signals are verified and a recovered clock out signal is provided.

Abstract: Disclosed is an electronic chip containing a plurality of electronic circuit partitions, distributed over the area of the chip, each including a processor core and a clock phase domain different from cores in other partitions of the chip. A source of same frequency, but different phase clock signals representing different clock domains, provides different phase signals to adjacent partitions for the purpose of reducing instantaneous magnitude switching currents. Intra-chip communication circuitry distributes control and data signals between partitions.

Abstract: The present invention provides for a phased locked loop. A capacitor has an associated leakage current. A differential circuit is coupled to the capacitor of a low pass filter. A voltage follower circuit is coupled to the output of the differential circuit. The gate of a field effect transistor (FET) is coupled to an output of the voltage follower circuit. A current mirror is coupled to the FET, the current mirror having a first source and a second source, wherein the second current mirror source is coupled to the drain of the FET, wherein an output of the first current mirror source is coupled to the capacitor. Through the employment of current mirror source, leakage charge within the capacitor is replaced.

Abstract: Disclosed is a PLL (Phase Lock Loop) reducing the lock-in-time of the phase lock loop by altering the impedance of the damping resistor portion of the included LPF (Low Pass Filter) as a function of the difference in frequency or phase between a PLL applied reference frequency and the output frequency provided by the VCO (Voltage Controlled Oscillator) portion of the PLL. This variable impedance is accomplished by introducing a feed forward path that switches a capacitor in and out of the circuit in accordance with the difference frequency. One embodiment uses a mixer to provide the difference frequency signal.

Abstract: The present invention provides for a divider circuit for reducing anomalous output timing pulses. A latch is coupled to the division selection line. A comparator is coupled to the division selection line. A first synchronizer coupled to the output of the latch. A frequency divider is coupled to the output of the synchronizer. A second synchronizer is coupled to the output of the comparator and the output of the frequency divider. There is feedback between the output of the second synchronizer and the enable input of the latch, the reset of the first synchronizer, the reset of the second synchronized, and the reset of the divide by n divider.

Abstract: The present invention provides for a low pass filter. A first capacitor, has a first associated leakage current. A second capacitor has a specified capacitance that is a fraction of the capacitance of the first capacitor, the second capacitor further having a second associated leakage current. A voltage follower circuit is coupled to the output of the first and second capacitor. First and second current sources are coupled to the voltage follower circuit. A bias current source is coupled the first current source. A current mirror is coupled to the second current source, and the current mirror is further coupled to at least the anode of the first capacitor, thereby generating replacement current of a capacitor within a low-pass filter.

Abstract: A system and method for reducing timing uncertainties in a serial data signal. A system may comprise a transmitter configured to transmit serial data to a receiver through a transmission medium. The receiver may comprise a retiming mechanism configured to sample the serial data using a particular phase of a clock at a point in time when the serial data signal may not be likely to experience jitter. The retiming mechanism may comprise a plurality of first units, e.g., flip-flops, where each of the first units is configured to sample the serial data using a particular phase of the clock. Each of the first units may be connected to a particular second unit, e.g., transmission gate. Each of the second units may be configured to output the value of the serial data sampled by the associated first unit upon activation. The data outputted may subsequently become part of the retimed data.

Abstract: An apparatus, a method, and a computer program are provided for correcting charge in a Phased Lock Loop (PLL). Typically, PLL's utilize a Low Pass Filter (LPF). However, as a result of improvement of Complimentary Metal-Oxide on a Semiconductor (CMOS) technology charge leakage has become prevalent within LPFs. As a result, the method, apparatus, and computer program provide a device and/or methodology for correcting for charge leakage.

Abstract: A method of extracting a clock signal from a data stream, by generating a plurality of multiphase clock signals, selecting one of the multiphase signals based on synchronization states identifying which of the multiphase clock signals is most closely aligned with the data stream, and sampling the data stream using the selected multiphase signal to produce a retimed data signal. The multiphase clock signals may be subharmonics of the data stream. The selecting step may include the determination of whether the multiphase clock signals are either early or late with respect to the data stream, particularly using D-type flip-flops. The synchronization states are used to define which of the rising edges of the multiphase clock signals is most closely aligned with an edge of the data stream. A multiphase voltage-controlled oscillator may be used to provide the multiphase clock signals.

Abstract: A method and an apparatus for testing a phase-locked loop (PLL) are provided. A fixed-level reference clock signal and a test feedback clock signal are applied to a phase-frequency detector (PFD) of the PLL to measure a minimum output frequency of a voltage-controlled oscillator (VCO) of the PLL. A test reference clock signal and a fixed-level feedback clock signal are applied to the PFD to measure a maximum output frequency of the VCO. The lock and capture range of the PLL is determined based on the maximum and minimum frequencies of the VCO.

Abstract: The present invention provides an integrated circuit. The integrated circuit has a plurality of chip areas. The integrated circuit also has a plurality of temperature sensors, at least one per chip area. The temperature sensors generate a voltage proportional to the measured temperature. A voltage comparator compares the voltage output of the plurality of temperature sensors. The voltage comparator is further employable to generate a signal if the difference between the voltages generated by the plurality of temperature sensors exceeds a threshold.

Abstract: Methods, systems and thermal sensing apparatus are provided that use bandgap voltage reference generators that do not use trimming circuitry. Further, circuits, systems, and methods in accordance with the present invention are provided that do not use large amounts of chip real estate and do not require a separate thermal sensing element.

Abstract: The present invention provides a method and an apparatus for generating a phase error signal from a reference signal and a feedback signal using a modified reset generation mechanism. An input circuit receives a reference signal and a feedback signal. A phase error detector circuit generates a phase error signal based on the reference signal and feedback signal. The input circuit is reset and, after a delay, the phase error detector circuit is reset. The delay is selected so that there is no jitter associated with the dead zone.

Abstract: A method of extracting a clock signal from a data stream, by generating a plurality of multiphase clock signals, creating error signals for each of the multiphase clock signals using the data stream, selecting at least one of the error signals based on retime state signals, correcting the multiphase clock signals using the error signal to produce corrected multiphase clock signals, and sampling the data stream using one of the corrected multiphase signals to produce a retimed data signal. The multiphase clock signals may be subharmonics of the data stream. In one embodiment, an UP error signal and a DN error signal are created for each of the multiphase clock signals, wherein the selecting step selects one of the UP error signals and one of the DN error signals, and the selected UP error signal and the selected DN error signal are applied to inputs of a charge pump to correct the clock signals. A multiphase voltage-controlled oscillator may be used to provide the multiphase clock signals.

Abstract: An interlace transceiver power management method and apparatus reduces power consumption when interface conditions will support a transceiver having reduced complexity. Characteristics of the receiver and/or transmitter are adjusted in conformity with one or more selection signals. An interface quality measurement circuit may provide the selection signal, so that the transceiver complexity is adjusted in response to measured interface conditions or an external pin or register bit may be coupled to a select input. The receiver complexity adjustment may include the receiver sampling depth, window width, resolution or equalization complexity or other characteristic having an impact on receiver circuit power consumption. The transmitter complexity may be equalization, transmitter power or other characteristic having an impact on transmitter circuit power consumption.

Abstract: An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a “time of day” value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.