Patents by Inventor Debra Bell
Debra Bell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10825492Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.Type: GrantFiled: May 20, 2019Date of Patent: November 3, 2020Assignee: Micron Technology, Inc.Inventors: Debra Bell, Kallol Mazumder
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Patent number: 10789182Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.Type: GrantFiled: December 24, 2019Date of Patent: September 29, 2020Assignee: Micron Technology, Inc.Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
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Publication number: 20200133893Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.Type: ApplicationFiled: December 24, 2019Publication date: April 30, 2020Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
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Patent number: 10521366Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.Type: GrantFiled: May 1, 2019Date of Patent: December 31, 2019Assignee: Micron Technology, Inc.Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
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Patent number: 10410696Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.Type: GrantFiled: December 28, 2017Date of Patent: September 10, 2019Assignee: Micron Technology, Inc.Inventors: Debra Bell, Kallol Mazumder
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Publication number: 20190272861Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.Type: ApplicationFiled: May 20, 2019Publication date: September 5, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Debra Bell, Kallol Mazumder
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Publication number: 20190258592Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
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Patent number: 10339071Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.Type: GrantFiled: December 10, 2018Date of Patent: July 2, 2019Assignee: Micron Technology, Inc.Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
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Patent number: 10268602Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.Type: GrantFiled: September 29, 2016Date of Patent: April 23, 2019Assignee: Micron Technology, Inc.Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
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Publication number: 20190087360Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.Type: ApplicationFiled: December 10, 2018Publication date: March 21, 2019Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B. Noyes
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Publication number: 20180122439Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.Type: ApplicationFiled: December 28, 2017Publication date: May 3, 2018Applicant: Micron Technology, Inc.Inventors: Debra Bell, Kallol Mazumder
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Publication number: 20180089113Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.Type: ApplicationFiled: September 29, 2016Publication date: March 29, 2018Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
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Patent number: 9892770Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.Type: GrantFiled: April 22, 2015Date of Patent: February 13, 2018Assignee: Micron Technology, Inc.Inventors: Debra Bell, Kallol Mazumder
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Publication number: 20160314823Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.Type: ApplicationFiled: April 22, 2015Publication date: October 27, 2016Inventors: Debra Bell, Kallol Mazumder
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Patent number: 9294105Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.Type: GrantFiled: November 19, 2013Date of Patent: March 22, 2016Assignee: Micron Technology, Inc.Inventors: Tyler J. Gomm, Debra Bell
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Patent number: 9286967Abstract: A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.Type: GrantFiled: May 7, 2015Date of Patent: March 15, 2016Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Debra Bell, Kallol Mazumder
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Publication number: 20150243344Abstract: A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.Type: ApplicationFiled: May 7, 2015Publication date: August 27, 2015Inventors: DEBRA BELL, KALLOL MAZUMDER
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Patent number: 9053815Abstract: A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.Type: GrantFiled: May 28, 2013Date of Patent: June 9, 2015Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Debra Bell, Kallol Mazumder
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Publication number: 20140355361Abstract: A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.Type: ApplicationFiled: May 28, 2013Publication date: December 4, 2014Applicant: NANYA TECHNOLOGY CORPORATIONInventors: DEBRA BELL, KALLOL MAZUMDER
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Publication number: 20140077852Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.Type: ApplicationFiled: November 19, 2013Publication date: March 20, 2014Applicant: Micron Technology, Inc.Inventors: Tyler J. Gomm, Debra Bell