Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Abstract: Some embodiments include a delay locked circuit having multiple paths. A first path measures a timing of a first clock signal during a measurement. A second path generates a second clock signal based on the first clock signal. The delay locked circuit periodically performs the measurement to adjust a timing relationship between the first and second clock signals. The time interval between one measurement and the next measurement is unequal to the cycle time of the first clock signal. Additional embodiments are disclosed.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: Some embodiments of the invention include a delay locked loop having a delay line for delaying an input signal. The input signal is generated from a first signal. A delay controller controls the delay line to adjusting the timing relationship between the first signal and the internal signal. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay line and the cycle time of the signal exiting the delay line. Other embodiments are described and claimed.

Abstract: A system unit including a processor unit and an input storage unit. The processor unit generates an input signal and a clock signal. The input storage unit receives the input signal and the clock signal. The input storage unit processes the clock signal to generate an input buffer enable signal. The input buffer enable signal changes from an inactive state to an active state a short time interval before at least one of the transitions of the clock signal. A method includes receiving a clock signal having a plurality of transitions at an input buffer unit, enabling the input buffer unit before each of the plurality of transitions, and disabling the input buffer unit after each of the plurality of transitions.

Abstract: Some embodiments of the invention includes a delay locked loop (DLL) having a coarse delay segment and fine delay segment. The coarse delay segment and the fine delay segment apply a coarse delay and a fine delay to a first clock signal to generate a second clock signal. The DLL adjusts the timing relationship between the first and second clock signals by adjusting the fine delay and the coarse delay. The DLL adjusts the fine delay based on the timing relationship between the first and second clock signals. The DLL adjusts the coarse delay based on both the fine delay being applied and the timing relationship between the first and second clock signals. Other embodiments are described and claims.

Abstract: A delay-lock loop includes a phase detector comparing the phase of a digital input signal to the phase of a feedback signal. The phase detector generates a corresponding control signal that is used to control the delay of a delay line. A multiplexer couples the input signal to the input of the delay line and thereafter couples a signal received from the output of the delay line to the input of the delay line so that the delay line functions as several individual delay lines. At least one digital signal that has propagated through the delay line is used as a feedback signal that is coupled from the output of the delay line to the phase detector by a signal router. The phase of the signal coupled to the phase detector by the router is therefore locked to the phase of the input signal.

Abstract: A delay-lock loop includes a phase detector comparing the phase of a digital input signal to the phase of a feedback signal. The phase detector generates a corresponding control signal that is used to control the delay of a delay line. A multiplexer couples the input signal to the input of the delay line and thereafter couples a signal received from the output of the delay line to the input of the delay line so that the delay line functions as several individual delay lines. At least one digital signal that has propagated through the delay line is used as a feedback signal that is coupled from the output of the delay line to the phase detector by a signal router. The phase of the signal coupled to the phase detector by the router is therefore locked to the phase of the input signal.

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Abstract: The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of the externally provided address signals are allowed to transition past address buffer circuitry.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: A memory device is configured to conserve electrical current by disabling the address lines provided to a memory bank when the address is not needed, such as during periods of automatic precharge. Because address data need not be provided while the memory bank is in an automatic precharge mode, the current used to keep the address lines active during this time may be conserved by suitably disabling the address lines for the duration of the automatic precharge. Disabling the various address lines may be accomplished by, for example, interposing an enabling element such as a field effect transistor within the address bus driver circuits leading to each memory bank, and by providing a suitable control signal to the enabling element to activate and deactivate the address line as needed.

Abstract: A delay locked loop (DLL) that applies an amount of delay to an external clock signal to generate multiple delayed signals. One of the delayed signals is selected as an internal clock signal. The multiple delayed signals have different delays in relation to the external clock signal. If a change in operating condition of the DLL occurs, such as a change in the supply voltage during an operational mode of the memory device such as an ACTIVE, a READ or a REFRESH mode, the DLL immediately selects another delayed signal among the multiple delayed signals as a new internal clock signal to compensate for the change before a phase detector of the DLL detects the change.