Abstract: A semiconductor memory device includes a memory cell array including a plurality of wordlines, a plurality of bitlines and a plurality of cells; a bitline decoder configured to couple a global bitline to one of the plurality of bitlines according to a bitline selection signal; a bitline driver configured to provide bitline current to the global bitline; a wordline decoder configured to couple a global wordline to one of the plurality of wordlines according to a wordline selection signal; a wordline driver configured to provide a wordline drive voltage to the global wordline during a write operation and to adjust the wordline drive voltage according to a write address; and a write control circuit configured to generate the wordline selection signal and the bitline selection signal, and to control the bitline decoder, the wordline decoder, and the bitline driver.

Abstract: A driving circuit includes an input circuit slice configured to convert a data signal into a first data signal and a second data signal having different DC components. The driving circuit also includes a driver slice configured to output driving current at an output node by generating push current or pull current according to the first data signal and the second data signal, wherein a magnitude of the push current or the pull current is variable.

Abstract: A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.

Abstract: An accelerator includes a key matrix register configured to store a key matrix, a query vector register configured to store a query vector; and a preprocessor configured to calculate similarities between the query vector and the key matrix.

Abstract: An integrated circuit may include: a first transmission line; a second transmission line; a first compensator circuit suitable for generating a first compensation signal by delaying and differentiating a signal transferred through the second transmission line; a second compensator circuit suitable for generating a second compensation signal by delaying and differentiating a signal transferred through the first transmission line; a first receiver circuit suitable for receiving the signal transferred through the first transmission line, and compensating for the signal transferred through the first transmission line using the first compensation signal; and a second receiver circuit suitable for receiving the signal transferred through the second transmission line, and compensating for the signal transferred through the second transmission line using the second compensation signal.

Abstract: An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.

Abstract: An impedance adjusting circuit includes: a first node coupled to a resistor; a first impedance unit having an impedance value determined based on a first impedance code and coupled between a first voltage terminal and a second node; a first switching unit suitable for electrically connecting the first node and the second node to each other in response to a clock; a first average voltage unit suitable for generating an average voltage of the first node; a first comparison unit suitable for comparing the average voltage of the first node with a first reference voltage to produce a comparison result of the first comparison unit; and a first code generation unit suitable for generating the first impedance code in response to the comparison result of the first comparison unit.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of wordlines, a plurality of bitlines and a plurality of cells; a bitline decoder configured to couple a global bitline to one of the plurality of bitlines according to a bitline selection signal; a bitline driver configured to provide bitline current to the global bitline; a wordline decoder configured to couple a global wordline to one of the plurality of wordlines according to a wordline selection signal; a wordline driver configured to provide a wordline drive voltage to the global wordline during a write operation and to adjust the wordline drive voltage according to a write address; and a write control circuit configured to generate the wordline selection signal and the bitline selection signal, and to control the bitline decoder, the wordline decoder, and the bitline driver.

Abstract: A data receiving circuit may include: a variable delay circuit suitable for generating a delayed strobe signal by delaying a strobe signal; a receiving circuit suitable for sampling data in synchronization with the delayed strobe signal; a phase shift circuit suitable for generating a shifted strobe signal by shifting a phase of the delayed strobe signal; a phase comparison circuit suitable for comparing phases of the data and the shifted strobe signal; and a delay adjusting circuit suitable for adjusting a delay value of the variable delay circuit in response to the phase comparison result of the phase comparison circuit.

Abstract: A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.

Abstract: A transceiver circuit may include: a first NMOS transistor suitable for puffing up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.

Abstract: In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.

Abstract: A data receiver circuit may include: a delay circuit suitable for delaying first and second strobe signals and generating delayed first and second strobe signals; a first receiver circuit suitable for sampling data in synchronization with the delayed first strobe signal; a second receiver circuit suitable for sampling the data in synchronization with the delayed second strobe signal; an enable signal generation circuit suitable for generating an enable signal indicating whether the data transitioned; a transition level generation circuit suitable for generating a transition level signal indicating a transition direction of the data; a phase shift circuit suitable for shifting the phase of the delayed first strobe signal by a set degree and generating a shifted first strobe signal; a sampling circuit suitable for sampling the data in synchronization with the shifted first strobe signal and generating a sampling result; and a control logic suitable for changing a delay value of the delay circuit in response to

Abstract: A semiconductor memory device includes a memory cell array including one or more memory cells each coupled between a wordline and a bitline, a sense amplifier configured to amplify a voltage of a global wordline, a wordline decoder including a plurality of wordline switches coupling the wordline and the global wordline, and a control circuit configured to control the wordline decoder and the sense amplifier.

Abstract: A display apparatus includes a display panel, a touch sensing unit, and a touch driving circuit. The touch sensing unit includes a transmission touch line. The touch driving circuit provides a touch driving signal to the transmission touch line. The touch driving circuit may include a switch group and a control switch group. The switch group may include a plurality of switch devices, each of which has one end connected to the transmission touch line. The control switch group may be connected to the other end of at least a portion of the switch devices, include a plurality of control switch devices and a capacitor device, and receive a driving voltage and a ground voltage. The touch driving signal has N voltage levels, where N is a natural number of 3 or more.

Abstract: A transceiver circuit may include: a first NMOS transistor suitable for pulling up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.

Abstract: An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

Abstract: In an embodiment, a duty cycle controller comprises a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal by a time less than the predetermined delay time and configured to delay the feedback clock signal by the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.

Abstract: An integrated circuit may include: a first transmission line; a second transmission line; a first compensator circuit suitable for generating a first compensation signal by delaying and differentiating a signal transferred through the second transmission line; a second compensator circuit suitable for generating a second compensation signal by delaying and differentiating a signal transferred through the first transmission line; a first receiver circuit suitable for receiving the signal transferred through the first transmission line, and compensating for the signal transferred through the first transmission line using the first compensation signal; and a second receiver circuit suitable for receiving the signal transferred through the second transmission line, and compensating for the signal transferred through the second transmission line using the second compensation signal.

Abstract: In an embodiment, a delay circuit comprises a delay loop controller outputting a signal obtained by operating a start signal and a delayed feedback clock signal output from outside the delay loop controller; and a loop counter configured to determine whether a predetermined delay time has elapsed since the start signal was input according to the delayed feedback clock signal and a predetermined loop count.