Patents by Inventor Deog-Kyoon Jeong

Deog-Kyoon Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Injection locked phase locked loop
    Patent number: 10044359
    Abstract: An injection locked phase locked loop includes an injection locked oscillator configured to generate an oscillation signal according to an injection signal and to generate a replica signal by replicating the oscillation signal when the injection signal is deactivated; a phase controller configured to generate a phase control signal according to a phase error signal; and an error detector configured to generate the phase error signal by comparing a phase of the oscillation signal and a phase of the replica signal, and to control a phase difference between the oscillation signal and the replica signal according to the phase control signal.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 7, 2018
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Sungwoo Kim, Han-Gon Ko, Suhwan Kim, Deog-Kyoon Jeong
  • Receiver resilient to noise input
    Patent number: 9991858
    Abstract: A receiver includes a signal receiving part suitable for outputting a signal corresponding to a reception signal that is received through an input terminal, and controlling a DC voltage of a signal to be outputted, according to an offset signal, an amplifying part suitable for amplifying and outputting an output of the signal receiving part, and a feedback control part suitable for controlling the offset signal according to an output of the amplifying part.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 5, 2018
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Sungphil Choi, Mino Kim, Suhwan Kim, Deog-Kyoon Jeong
  • RECEIVER RESILIENT TO NOISE INPUT
    Publication number: 20180062594
    Abstract: A receiver includes a signal receiving part suitable for outputting a signal corresponding to a reception signal that is received through an input terminal, and controlling a DC voltage of a signal to be outputted, according to an offset signal, an amplifying part suitable for amplifying and outputting an output of the signal receiving part, and a feedback control part suitable for controlling the offset signal according to an output of the amplifying part.
    Type: Application
    Filed: May 2, 2017
    Publication date: March 1, 2018
    Inventors: Sungphil CHOI, Mino KIM, Suhwan KIM, Deog-Kyoon JEONG
  • RECEIVER RESILIENT TO NOISE INPUT
    Publication number: 20180041209
    Abstract: A receiver includes a first input buffering circuit configured to output a first signal by comparing an input signal and a first offset signal; a second input buffering circuit configured to output a second signal by comparing the input signal and a second offset signal; and a signal mixing circuit configured to output an output signal with a corrected duty ratio by combining the first signal and the second signal.
    Type: Application
    Filed: June 12, 2017
    Publication date: February 8, 2018
    Inventors: Mino KIM, Suhwan KIM, Deog-Kyoon JEONG
  • INJECTION-LOCKED OSCILLATOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    Publication number: 20170366195
    Abstract: An injection-locked oscillator includes an oscillator and an injection circuit. The oscillator includes a first oscillation node through which a first oscillation signal is output and a second oscillation node through which a second oscillation signal is output, the second oscillation signal having a phase opposite to that of the first oscillation signal. The injection circuit provides an injection current between the first oscillation node and the second oscillation node according to a reference signal. The injection circuit includes a charging element configured to be charged or discharged in response to a reference signal and to provide the injection current between the first oscillation node and the second oscillation node.
    Type: Application
    Filed: April 21, 2017
    Publication date: December 21, 2017
    Inventors: Sungwoo KIM, Sungyong CHO, Hankyu CHI, Suhwan KIM, Deog-Kyoon JEONG
  • TRIANGULAR WAVE GENERATOR
    Publication number: 20170338806
    Abstract: A triangular wave generator includes a wave generator configured to generate a triangular wave according to a clock signal and a control signal. The triangular wave generator further includes a wave controller configured to adjust a value of the control signal in a correction mode. The control signal includes a first bias control signal, a second bias control signal, and a capacitance control signal.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 23, 2017
    Inventors: Joohyung CHAE, Hankyu CHI, Suhwan KIM, Deog-Kyoon JEONG
  • Semiconductor device and operating method thereof
    Patent number: 9628060
    Abstract: A semiconductor device may include: a variable delay circuit configured to delay a data strobe signal according to a delay control signal and output a delayed data strobe signal; a data sampler configured to compare a level of a reference voltage and a value of a data signal in synchronization with the delayed data strobe signal, and determine a logic level of the value of the data signal, the data signal having a training pattern; and a control circuit configured to determine a delay amount of the data strobe signal and generate the delay control signal and the reference voltage according to an output signal of the data sampler.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 18, 2017
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Seok-Min Ye, Suhwan Kim, Deog-Kyoon Jeong
  • Multi-channel delay locked loop
    Patent number: 9564907
    Abstract: A multi-channel delay locked loop includes a global delay locked loop and a plurality of local delay locked loops. The global delay locked loop is configured to lock an input clock signal and output a global delay control signal corresponding to a delay amount of the input clock signal during a locking operation. Each of the plurality of local delay locked loops is configured to output a channel clock signal by locking the input clock signal, and initialize the delay amount of the input clock signal according to the global delay control signal.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: February 7, 2017
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Joo-Hyung Chae, Suhwan Kim, Deog-Kyoon Jeong
  • Data receiver
    Patent number: 9369265
    Abstract: A data receiver includes a sampling clock generator configured to generate a sampling clock signal from an internal clock signal according to a data strobe signal, and a sampler configured to sample a data signal according to the sampling clock signal.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: June 14, 2016
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Gi-Moon Hong, Suhwan Kim, Deog-Kyoon Jeong
  • SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
    Publication number: 20160149565
    Abstract: A semiconductor device may include: a variable delay circuit configured to delay a data strobe signal according to a delay control signal and output a delayed data strobe signal; a data sampler configured to compare a level of a reference voltage and a value of a data signal in synchronization with the delayed data strobe signal, and determine a logic level of the value of the data signal, the data signal having a training pattern; and a control circuit configured to determine a delay amount of the data strobe signal and generate the delay control signal and the reference voltage according to an output signal of the data sampler.
    Type: Application
    Filed: August 28, 2015
    Publication date: May 26, 2016
    Inventors: Seok-Min YE, Suhwan KIM, Deog-Kyoon JEONG
  • Equalizer and operating method thereof
    Patent number: 9219628
    Abstract: An equalizer includes a sampler configured to sample an edge and data of an input signal or an induced signal obtained from the input signal, a clock generator configured to generate an edge clock used to decide sampling timing of the edge and a data clock used to decide sampling timing of the data based on the sampled edge and the sampled data, and a controller configured to control the sampling timing of the edge and the sampling timing of the data based on the sampled edge and the sampled data.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: December 22, 2015
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Seok-Min Ye, Deog-Kyoon Jeong
  • Receiver, system including the same, and calibration method thereof
    Patent number: 9059825
    Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 16, 2015
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Han-Kyu Chi, Taek-Sang Song, Seok-Min Ye, Gi-Moon Hong, Woo-Rham Bae, Min-Seong Chu, Deog-Kyoon Jeong, Su-Hwan Kim
  • RECEIVER, SYSTEM INCLUDING THE SAME, AND CALIBRATION METHOD THEREOF
    Publication number: 20150139289
    Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.
    Type: Application
    Filed: September 26, 2014
    Publication date: May 21, 2015
    Inventors: Han-Kyu CHI, Taek-Sang SONG, Seok-Min YE, Gi-Moon HONG, Woo-Rham BAE, Min-Seong CHU, Deog-Kyoon JEONG, Su-Hwan KIM
  • Coarse lock detector
    Patent number: 9000814
    Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Moon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi, Deog-Kyoon Jeong
  • COARSE LOCK DETECTOR
    Publication number: 20140312941
    Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 23, 2014
    Inventors: Moon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi, Deog-Kyoon Jeong
  • Level-down shifter
    Patent number: 8829969
    Abstract: A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: September 9, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Moon-Sang Hwang, Won-Jun Choe, Hyun-Chang Kim, Deog-Kyoon Jeong
  • EQUALIZER AND OPERATING METHOD THEREOF
    Publication number: 20140140385
    Abstract: An equalizer includes a sampler configured to sample an edge and data of an input signal or an induced signal obtained from the input signal, a clock generator configured to generate an edge clock used to decide sampling timing of the edge and a data clock used to decide sampling timing of the data based on the sampled edge and the sampled data, and a controller configured to control the sampling timing of the edge and the sampling timing of the data based on the sampled edge and the sampled data.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 22, 2014
    Applicants: SNU R&DB FOUNDATION, SK HYNIX INC.
    Inventors: Seok-Min YE, Deog-Kyoon JEONG
  • Coarse lock detector
    Patent number: 8729937
    Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 20, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Moon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi, Deog-Kyoon Jeong
  • Coarse lock detector and delay-locked loop including the same
    Patent number: 8587355
    Abstract: A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: November 19, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Moon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi, Deog-Kyoon Jeong
  • LIQUID CRYSTAL DISPLAY DEVICE, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR MANUFACTURING SUBSTRATE FOR ALIGNMENT OF LIQUID CRYSTAL
    Publication number: 20130027640
    Abstract: A method for manufacturing a substrate for alignment of a liquid crystal may include: forming a vertical alignment layer on a substrate; performing an alignment process on the vertical alignment layer in a first direction; forming a protective layer at a partial region of the vertical alignment layer; performing an alignment process on other regions of the vertical alignment layer in a second direction; and removing the protective layer. A liquid crystal display device manufactured using the substrate for alignment of a liquid crystal ensures wide viewing angle and alignment stability with relatively simple processes as compared with the conventional vertically aligned (VA) mode liquid crystal display device.
    Type: Application
    Filed: August 4, 2010
    Publication date: January 31, 2013
    Applicant: SNU R&DB FOUNDATION
    Inventors: Sin-Doo Lee, Deog-Kyoon Jeong, Jun-Hee Na